Resistance random access memory having common source line

Abstract

A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.

1 . A method writing data having a first state and a second state to a selected memory cell of a resistance random access memory (RRAM) through first and second write paths formed in mutually opposite directions, the RRAM having a plurality of word lines, a plurality of bit lines, a memory cell array having a plurality of memory cells disposed in a matrix, each having an access transistor and a resistive memory device, and a plurality of source lines disposed between two word lines and extending in a same direction as the word lines, and being connected to a source terminal of a corresponding access transistor having gate terminals connected to corresponding two word lines, the method comprising:
 applying a positive source voltage to a selected source line;   applying a word line drive voltage to a selected word line among the plurality of word lines; and   applying a voltage at least twice the level of the positive source voltage to a selected bit line among the plurality of bit lines via the first write path when writing data having the first state in the selected memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the selected memory cell.   
     
     
         2 . The method of  claim 1 , wherein when data having the first state has a logic level ‘1’ and data having the second state has a logic level ‘0’. 
     
     
         3 . The method of  claim 1 , wherein the resistive memory device comprises top and bottom electrodes, and the data is written to the selected memory cell by changing a resistance value associated with the resistive memory device using a voltage pulse flowing through the top and bottom electrodes. 
     
     
         4 . The method of  claim 1 , wherein the memory device comprises a plurality of the source lines defining a source line shared structure of a memory cell block of the memory cell array. 
     
     
         5 . The method of  claim 1 , wherein the resistive memory device further comprises a chrome-doped SrZrO3 material disposed between a top and bottom electrodes. 
     
     
         6 . The method of  claim 1 , wherein the resistive memory device further comprises a thin film of polycrystalline PrCaMnO3 material disposed between a top and bottom electrodes.