US2011128170A1PendingUtilityA1

Semiconductor devices, a system including semiconductor devices and methods thereof

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Assignee: BAE SEUNG-JUNPriority: May 27, 2006Filed: Oct 12, 2010Published: Jun 2, 2011
Est. expiryMay 27, 2026(expired)· nominal 20-yr term from priority
G06F 13/00H04L 25/14H04L 25/03866H03K 19/00346H04L 25/4908
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Claims

Abstract

Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Claims

exact text as granted — not AI-modified
1 . A method of reducing noise, comprising:
 receiving first parallel data, the first parallel data including a first plurality of bits arranged in a first order;   scrambling the first plurality of bits included among the first parallel data to obtain second parallel data having the first plurality of bits arranged in a second order; and   generating a balance code having a second plurality of bits by adding at least one additional bit to the first plurality of bits and adjusting a logic level of at least one of the first plurality of bits such that a difference between a first number of the second plurality of bits equal to a first logic level and a second number of the second plurality of bits equal to a second logic level is below a threshold.

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