US2011143518A1PendingUtilityA1

Heterogeneous integration of low noise amplifiers with power amplifiers or switches

41
Assignee: BRAR BERINDERPriority: Sep 14, 2006Filed: Feb 22, 2011Published: Jun 16, 2011
Est. expirySep 14, 2026(~0.2 yrs left)· nominal 20-yr term from priority
H10D 84/05H10D 84/01
41
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Abstract

A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate having a first end and a second end, a conducting layer above the first end of the substrate, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.

Claims

exact text as granted — not AI-modified
1 . A method for heterogeneously integrating a power amplifier or switch with a low-noise amplifier, comprising the steps of:
 depositing a first active layer above a substrate suitable for high electron mobility transistors;   implanting ions in a first region of the first active layer to form an isolation implant;   depositing a second active layer above the isolation implant; and   depositing metal contacts on the second active layer and on a second region of the first active layer.   
     
     
         2 . The method of  claim 1 , wherein the substrate is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb). 
     
     
         3 . The method of  claim 1 , further comprising depositing a first buffer layer on the substrate before depositing the first active layer. 
     
     
         4 . The method of  claim 1 , further comprising depositing a second buffer layer on the isolation implant and substantially within the first region of the first active layer. 
     
     
         5 . The method of  claim 1 , wherein the first active layer actuates the power amplifier or switch, and the second active layer activates the low noise amplifier. 
     
     
         6 . The method of  claim 5 , further comprising:
 depositing a first buffer layer on the substrate before depositing the first active layer, the first buffer layer formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof; and   depositing a second buffer layer on isolation implant and substantially within the first region of the first active layer, the second buffer layer formed with Aluminum Gallium Antimonide (AlGaSb),   wherein the first active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer, and   wherein the second active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.   
     
     
         7 . The method of  claim 1 , wherein the second active layer actuates the power amplifier or switch, and the first active layer activates the low noise amplifier. 
     
     
         8 . The method of  claim 7 , further comprising:
 depositing a first buffer layer on the substrate before depositing the first active layer, the first buffer layer formed with Aluminum Gallium Antimonide (AlGaSb); and   depositing a second buffer layer on isolation implant and substantially within the first region of the first active layer, the second buffer layer formed with a material selected from a group consisting of Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), and combinations thereof,   wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer, and   wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.

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