Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits

Abstract

An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

1 . A method of driving a nonvolatile memory device, the method comprising:
 preparing a nonvolatile memory device having a plurality of nonvolatile memory cells correspondingly coupled to first lines and second lines, and a sensing node coupled to the first lines;   supplying a write voltage to the nonvolatile memory cells through the sensing node so as to write data;   discharging the sensing node;   precharging the sensing node;   clamping the sensing node to a clamp voltage level; and   sensing a change in the voltage level of the sensing node and reading data stored in the nonvolatile memory cell while applying a compensating current to the sensing node.   
     
     
         2 . The method of  claim 1 , wherein the write voltage includes a set voltage for writing set data into the nonvolatile memory cell and a reset voltage for writing reset data into the nonvolatile memory cell, and
 the set voltage has a higher voltage level than the reset voltage.   
     
     
         3 . The method of  claim 2 , wherein the clamp voltage has a lower voltage level than the reset voltage. 
     
     
         4 . A method of operating a nonvolatile memory device, comprising:
 programming a first nonvolatile memory cell in the nonvolatile memory device by electrically coupling a sensing node held at a first write voltage to a first bit line electrically coupled to the first nonvolatile memory cell; and   reading a state of the first nonvolatile memory cell by:
 discharging the sensing node to a discharged voltage level; then 
 precharging the sensing node from the discharged voltage level to a first read voltage level; and then 
 sensing a change in voltage of the sensing node from the first read voltage level by electrically coupling the sensing node to the first bit line while concurrently supplying the sensing node with a compensating current. 
   
     
     
         5 . The method of  claim 4 , wherein the compensating current has a magnitude sufficient to hold the sensing node at about the first read voltage level when the first nonvolatile cell is programmed into a first state, but insufficient to prevent a voltage of the sensing node from dropping below the first read voltage level when the first nonvolatile memory cell is programmed into a second state. 
     
     
         6 . The method of  claim 5 , wherein the first state is a reset state and the second state is a set state. 
     
     
         7 . The method of  claim 5 , wherein said sensing comprises supplying compensating current through a PMOS transistor. 
     
     
         8 . The method of  claim 4 , wherein said sensing comprises comparing a voltage of the sensing node to a reference voltage; and wherein the compensating current has a magnitude sufficient to hold the sensing node above the reference voltage level when the first nonvolatile cell is programmed into a first state, but insufficient to prevent a voltage of the sensing node from dropping below the reference voltage when the first nonvolatile memory cell is programmed into a second state. 
     
     
         9 . The method of  claim 4 , wherein said programming comprises supplying a set or reset voltage to a first terminal of a comparator concurrently with feeding back a voltage of the sensing node to a second terminal of the comparator. 
     
     
         10 . A method of operating a nonvolatile memory device, comprising:
 programming a first uni-directional resistive memory cell in the nonvolatile memory device into one of a set state and a reset state; and   reading a state of the first uni-directional resistive memory cell by sensing a change in voltage of a sensing node electrically coupled thereto relative to a reference voltage, said reading comprising supplying the sensing node with a positive compensating current having a magnitude sufficient to hold the sensing node at a voltage greater than the reference voltage when the first uni-directional resistive memory cell is in the reset state, but insufficient to prevent a voltage of the sensing node from being pulled below the reference voltage when the first uni-directional resistive memory cell is in the set state and sinking current from the sensing node.   
     
     
         11 . The method of  claim 10 , wherein said reading comprises supplying the compensating current through a PMOS transistor. 
     
     
         12 . The method of  claim 10 , wherein said programming comprises supplying a set or reset voltage to a first terminal of a comparator concurrently with feeding back a voltage of the sensing node to a second terminal of the comparator. 
     
     
         13 . The method of  claim 10 , wherein said reading further comprises sequentially discharging and then precharging the sensing node in advance of supplying the sensing node with the compensating current.