Suppressing power supply noise using data scrambling in double data rate memory systems

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.

1 . An integrated circuit comprising:
 a transmit data path to transmit data to one or more memory devices, the transmit data path including,
 scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other, 
 XOR logic having as a first input the N pseudo random outputs of the scrambling logic and having as a second input M data bits, the XOR logic to output, in parallel, M scrambled bits, and 
 a transmitter coupled with the XOR logic, the transmitter to transmit the M scrambled bits to the one or more memory devices via a memory interconnect, wherein the M scrambled bits have a substantially pseudo random pattern. 
   
     
     
         2 . The integrated circuit of  claim 1 , wherein the scrambling logic comprises a parallel linear feedback shift register (LFSR). 
     
     
         3 . The integrated circuit of  claim 2 , wherein a seed for the parallel LFSR is based, at least in part, on a memory address associated with the M scrambled bits. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the seed for the parallel LFSR is based, at least in part, on a column address associated with the M scrambled bits. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the seed for the parallel LFSR is scrambled prior to use. 
     
     
         6 . The integrated circuit of  claim 4 , wherein the parallel LFSR is to be seeded at the beginning of each write burst. 
     
     
         7 . The integrated circuit of  claim 2 , wherein the parallel LFSR is based, at least in part, on the polynomial: X 16 +X 13 +X 10 +X 9 +X 8 +X 4 +1. 
     
     
         8 . The integrated circuit of  claim 1 , further comprising:
 a receive data path to receive data from the one or more memory devices, the receive data path including,
 a receiver to receive, in parallel, M scrambled bits from the memory interconnect, 
 unscrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other, and 
 XOR logic having as a first input the M scrambled bits from the memory interconnect and having as a second input the N pseudo random outputs of the unscrambling logic, the XOR logic to output, in parallel, M unscrambled bits. 
   
     
     
         9 . The integrated circuit of  claim 8 , wherein the unscrambling logic comprises a parallel linear feedback shift register (LFSR). 
     
     
         10 . The integrated circuit of  claim 9 , wherein a seed for the parallel LFSR is based, at least in part, on a column address associated with the M scrambled bits. 
     
     
         11 . The integrated circuit of  claim 4 , wherein the parallel LFSR is to be seeded at the beginning of each read burst. 
     
     
         12 . A method comprising:
 issuing a write command to instruct a transmit data path to write a burst of data to memory;   generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on the write command;   scrambling M transmit bits based, at least in part, on the N pseudo random outputs to create M scrambled bits; and   transmitting the M scrambled bits to one or more memory devices via a memory interconnect.   
     
     
         13 . The method of  claim 12 , wherein generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on the write command comprises:
 generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on a memory address associated the burst of data.   
     
     
         14 . The method of  claim 13 , wherein generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on a memory address associated the burst of data comprises:
 generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on a column address associated the burst of data.   
     
     
         15 . The method of  claim 12 , further comprising:
 issuing a read command to instruct a receive data path to read a burst of data from memory;   generating, in parallel, N pseudo random outputs that are uncorrelated with each other based, at least in part, on the read command;   receiving M scrambled bits from one or more memory devices via a memory interconnect; and   unscrambling the M scrambled bits based, at least in part, on the N pseudo random outputs to create M unscrambled bits.   
     
     
         16 . A system comprising:
 one or more dynamic random access memory devices (DRAMs); and   an integrated circuit coupled with the one or more DRAMs via a memory interconnect, the integrated circuit having a transmit data path to transmit data to the one or more memory devices, the transmit data path including,
 scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other, 
 XOR logic having as a first input the N pseudo random outputs of the scrambling logic and having as a second input M data bits, the XOR logic to output, in parallel, M scrambled bits, and 
 a transmitter coupled with the XOR logic, the transmitter to transmit the M scrambled bits to the one or more memory devices via the memory interconnect, wherein the M scrambled bits have a substantially pseudo random pattern. 
   
     
     
         17 . The system of  claim 16 , wherein the scrambling logic comprises a parallel linear feedback shift register (LFSR). 
     
     
         18 . The system of  claim 17 , wherein a seed for the parallel LFSR is based, at least in part, on a memory address associated with the M scrambled bits. 
     
     
         19 . The system of  claim 18 , wherein the seed for the parallel LFSR is scrambled prior to use. 
     
     
         20 . The system of  claim 17 , wherein the parallel LFSR is based, at least in part, on the polynomial: X 16 +X 13 +X 10 +X 9 +X 8 +X 4 +1. 
     
     
         21 . The system of  claim 16 , wherein the integrated circuit further comprises:
 a receive data path to receive data from the one or more memory devices, the receive data path including,
 a receiver to receive, in parallel, M scrambled bits from the memory interconnect, 
 unscrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other, and 
 XOR logic having as a first input the M scrambled bits from the memory interconnect and having as a second input the N pseudo random outputs of the unscrambling logic, the XOR logic to output, in parallel, M unscrambled bits. 
   
     
     
         22 . The system of  claim 21 , wherein the unscrambling logic comprises a parallel linear feedback shift register (LFSR). 
     
     
         23 . The system of  claim 22 , wherein a seed for the parallel LFSR is based, at least in part, on a column address associated with the M scrambled bits. 
     
     
         24 . The system of  claim 23 , wherein the parallel LFSR is to be seeded at the beginning of each read burst.