Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening

Abstract

Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

1 . A method of forming an electronic package, said method comprising:
 providing a substrate;   forming a solder pad on said substrate;   forming a solder resist layer on said substrate covering said solder pad;   forming a via through said solder resist layer to said solder pad such that said via has a first diameter;   forming a metal layer, wherein said forming of said metal layer comprises:
 forming a lower portion of said metal layer adjacent said solder pad so as to fill said via; and 
 forming an upper portion of said metal layer above said lower portion and extending laterally on a top surface of said solder resist layer outside said via such that said upper portion has a second diameter greater than said first diameter; and 
   electrically and mechanically connecting a chip to said substrate by creating a solder joint between said metal layer and a corresponding conductive pad on said chip.   
     
     
         2 . The method according to  claim 1 , wherein said forming of said metal layer further comprises forming said metal layer such that said second diameter ranges between approximately 1.05 and 10 times said first diameter. 
     
     
         3 . The method according to  claim 1 , wherein said forming of said metal layer further comprises forming said metal layer such that said second diameter is at least 10 microns greater than said first diameter. 
     
     
         4 . The method according to  claim 1 , wherein said creating of said solder joint comprises creating a lead-free solder joint that is essentially void-free by one of forming said solder joint without solder paste and forming said solder joint with solder paste on said upper portion of said metal layer outside said via. 
     
     
         5 . The method according to  claim 1 , wherein said forming of said metal layer comprises using a mushroom-plating technique to form a copper layer that fills and overflows said via such that said copper layer extends laterally on said top surface of said solder resist layer outside said via. 
     
     
         6 . A method of forming an electronic package, said method comprising:
 providing a substrate;   forming a solder pad on said substrate;   forming a solder resist layer on said substrate covering said solder pad;   forming a via through said solder resist layer to said solder pad such that said via has a first diameter;   forming a metal layer, wherein said forming of said metal layer comprises:
 forming a lower portion of said metal layer adjacent said solder pad so as to fill said via; and 
 forming an upper portion of said metal layer above said lower portion and extending laterally on top surface of said solder resist layer outside said via such that said upper portion has a second diameter greater than said first diameter; and 
   forming at least one ball limiting metallurgy layer on said metal layer; and   electrically and mechanically connecting a chip to said substrate by creating a solder joint between said at least one ball limiting metallurgy layer and a corresponding conductive pad on said chip.   
     
     
         7 . The method according to  claim 6 , wherein said forming of said metal layer comprises forming said metal layer such that said second diameter ranges between approximately 1.05 and 10 times said first diameter. 
     
     
         8 . The method according to  claim 6 , wherein said forming of said metal layer further comprises forming said metal layer such that said second diameter is at least 10 microns greater than said first diameter. 
     
     
         9 . The method according to  claim 6 , wherein said creating of said solder joint comprises creating a lead-free solder joint that is an essentially void-free by one of forming said solder joint without solder paste and forming said solder joint with solder paste on said upper portion of said metal layer outside said via. 
     
     
         10 . The method according to  claim 6 , wherein said forming of said metal layer comprises using a mushroom-plating technique to form a copper layer that fills and overflows said via such that said copper layer extends laterally on said top surface of said solder resist layer outside said via. 
     
     
         11 . A method of forming a chip carrier comprising:
 providing a substrate;   forming a first conductive pad on said substrate;   forming a solder resist layer on said substrate covering said first conductive pad, said solder resist layer having a top surface;   forming a via, having a first diameter, and extending through said solder resist layer to said first conductive pad;   forming an electroplated metal layer having a lower portion and an upper portion, said lower portion being formed to be immediately adjacent to said first conductive pad and filling said via, and said upper portion being formed above said lower portion and having a second diameter greater than said first diameter such that said upper portion extends laterally over and physically contacts said top surface of said solder resist layer, said upper portion being formed to have a first side adjacent to said top surface and a second side opposite said first side, said second side being formed to be curved such that a thickness of said upper portion tapers from a center of said upper portion to an outer edge of said upper portion; and   forming a plurality of ball limiting metallurgy layers covering said second side of said upper portion of said metal layer;   forming a semiconductor chip comprising a second conductive pad; and   forming a solder layer extending between said ball limiting metallurgy layers and said second conductive pad so as to electrically connect said semiconductor chip to said chip carrier.   
     
     
         12 . The method according to  claim 11 , said second diameter ranging between approximately 1.05 and 10 times said first diameter. 
     
     
         13 . The method according to  claim 11 , said second diameter being at least 10 microns greater than said first diameter. 
     
     
         14 . The method according to  claim 11 , said solder layer comprising a lead-free solder that is essentially void-free and said electroplated metal layer comprising an electroplated copper layer. 
     
     
         15 . The method according to  claim 11 , said ball limiting metallurgy layers comprising an adhesion layer, a barrier layer, and a bonding layer.