Inventor · disambiguated record
Virendra R. Jadhav
Also filed as: JADHAV VIRENDRA · JADHAV VIRENDRA R
24 granted patents·2 pending applications·182 citations·filing 2002–2019
96Inventor score
Top patents by PatentIndex Score
26 records- 0194US9472520B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2012·Granted Oct 18, 2016·14 cites·19 claims
- 0293US11244917B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Feb 8, 2022·4 cites·11 claims
- 0393US9366591B2Determining magnitude of compressive loadingIBM·Filed 2014·Granted Jun 14, 2016·10 cites·12 claims
- 0492US8421217B2Achieving mechanical and thermal stability in a multi-chip packageCASEY JON A·Filed 2012·Granted Apr 16, 2013·19 cites·19 claims
- 0592US8202765B2Achieving mechanical and thermal stability in a multi-chip packageCASEY JON A·Filed 2009·Granted Jun 19, 2012·28 cites·22 claims
- 0691US10403590B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2017·Granted Sep 3, 2019·4 cites·9 claims
- 0791US10037062B1Thermal venting device with pressurized plenumMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Jul 31, 2018·10 cites·15 claims
- 0890US7812438B2Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packagingIBM·Filed 2008·Granted Oct 12, 2010·21 cites·11 claims
- 0988US10396051B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2017·Granted Aug 27, 2019·3 cites·13 claims
- 1087US8293587B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2007·Granted Oct 23, 2012·9 cites·19 claims
- 1182US6703704B1Stress reducing stiffener ringIBM·Filed 2002·Granted Mar 9, 2004·35 cites·22 claims
- 1281US8794079B2Determining magnitude of compressive loadingBODENWEBER PAUL F·Filed 2011·Granted Aug 5, 2014·3 cites·9 claims
- 1381US7875972B2Semiconductor device assembly having a stress-relieving buffer layerIBM·Filed 2009·Granted Jan 25, 2011·10 cites·17 claims
- 1478US8957531B2Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivityBERNIER WILLIAM E·Filed 2011·Granted Feb 17, 2015·4 cites·17 claims
- 1568US11094657B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Aug 17, 2021·0 cites·14 claims
- 1668US8717043B2Determining thermal interface material (TIM) thickness changeBODENWEBER PAUL F·Filed 2011·Granted May 6, 2014·2 cites·19 claims
- 1766US11171102B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Nov 9, 2021·0 cites·13 claims
- 1862US9640501B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2014·Granted May 2, 2017·0 cites·19 claims
- 1960US7952207B2Flip-chip assembly with organic chip carrier having mushroom-plated solder resist openingIBM·Filed 2007·Granted May 31, 2011·2 cites·15 claims
- 2058US9899279B2Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivityIBM·Filed 2014·Granted Feb 20, 2018·0 cites·10 claims
- 2156US10699972B2Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivityIBM·Filed 2017·Granted Jun 30, 2020·0 cites·16 claims
- 2256US9111816B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2012·Granted Aug 18, 2015·0 cites·18 claims
- 2355US7088008B2Electronic package with optimized circuitization patternIBM·Filed 2003·Granted Aug 8, 2006·4 cites·25 claims
- 2447US2011195543A1Flip-chip assembly with organic chip carrier having mushroom-plated solder resist openingIBM·Filed 2011·Application pending·0 cites
- 2543US7819027B2Method and structure for a pull test for controlled collapse chip connections and ball limiting metallurgyIBM·Filed 2007·Granted Oct 26, 2010·0 cites·5 claims
- 2643US2008142968A1Structure for controlled collapse chip connection with a captured pad geometryIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →