Semiconductor device and manufacturing method thereof

Abstract

An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10 a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

1 - 15 . (canceled) 
     
     
         16 . A semiconductor device, comprising:
 an insulating film formed on a main surface of a prescribed substrate;   a semiconductor layer of a first conductivity type formed on said insulating film;   an isolation region, continuously surrounding a prescribed region to be an element forming region in said semiconductor layer, formed from the surface of said semiconductor layer to a surface of said insulating film and having an inner sidewall and an outer sidewall;   a first impurity region of a second conductivity type formed continuously to be in contact with an entire surface of said inner sidewall of said isolation region, positioned between a portion of said semiconductor layer positioned in said prescribed region and said isolation region; and   an element formed in said prescribed region, the element being a bipolar transistor including:
 an emitter region, 
 a collector region, and 
 a base region, 
   wherein said first impurity region includes either said base region or said collector region.   
     
     
         17 . The semiconductor device according to  claim 16 , wherein the first impurity region and the second impurity region are held at a same potential. 
     
     
         18 . The semiconductor device according to  claim 17 , wherein
 said first impurity region is formed to have a prescribed impurity concentration so that an end of a depletion layer extending from an interface between said first impurity region and a portion of said semiconductor layer positioned in said prescribed region does not reach said isolation region during an operation.   
     
     
         19 . The semiconductor device according to  claim 17 , wherein
 said first impurity region has an impurity concentration set to be higher than that of said element forming region.