Universal structure for memory cell characterization

Abstract

An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type and are not connected together, where each node in the first storage node set is connected to a port in the first port set, where each node in the second storage node set is connected to a port in the second port set, where each of the other nodes is connected to one of the other ports, and where each of the other ports is connected to one and only one of the other nodes.

1 . An integrated circuit comprising a first structure, wherein said first structure comprises a first memory base cell, a first port set, and a set of other ports, wherein said first memory base cell comprises a plurality of circuit elements, a first storage node set, and a set of other nodes, wherein said first storage node set is the only storage node set in said first memory base cell, wherein each of said circuit elements has a plurality of terminals, wherein each node in said first storage node set and said set of other nodes is connected to at least one of said terminals, wherein said set of other nodes comprises a first data node for accessing said first storage node set, a first access control node for controlling the access of said first storage node set, and a reference node for said first storage node set, wherein each node in said first storage node set is connected to a port in said first port set, wherein each of said other nodes is connected to one of said other ports, and wherein each of said other ports is connected to one and only one of said other nodes. 
     
     
         2 . The integrated circuit of  claim 1 , wherein said set of other nodes further comprises a second data node for accessing said first storage node set and a second access control node for controlling the access of said first storage node set. 
     
     
         3 . The integrated circuit of  claim 1 , wherein said plurality of circuit elements comprises a transistor having a body terminal, and wherein said set of other nodes further comprises a body node connected to said body terminal. 
     
     
         4 . The integrated circuit of  claim 1 , further comprising a plurality of other structures each being selected from the group consisting of a probe pad, a bond pad, and a bump, wherein each port in said first port set and said set of other ports is connected to one of said other structures, and wherein each of said other structures is connected to one and only one port in said first port set and said set of other ports. 
     
     
         5 . The integrated circuit of  claim 1 , wherein said first structure further comprises a plurality of other memory base cells and a third port set, wherein said first memory base cell and said plurality of other memory base cells together form an array having substantially the same configuration as a memory array, wherein each of said other memory base cells is substantially the same as said first memory base cell, wherein each of said other memory base cells is adjacent to said first memory base cell, and wherein at least one of the access control nodes in said other memory base cells and nodes in the storage node sets in said other memory base cells is connected to a port in said third port set. 
     
     
         6 . The integrated circuit of  claim 1 , wherein at least two nodes in said first storage node set are connected to a same port in said first port set. 
     
     
         7 . The integrated circuit of  claim 1 , wherein said first port set consists of one and only one port. 
     
     
         8 . An integrated circuit comprising a memory cell formed based on data collected from a characterization of the first structure in the integrated circuit of  claim 1 . 
     
     
         9 . An integrated circuit comprising:
 a first structure comprising a first memory base cell, a first port set, and a set of other ports, wherein said first memory base cell comprises a plurality of circuit elements, a first storage node set, and a set of other nodes, wherein said first storage node set is the only storage node set in said first memory base cell, wherein each of said circuit elements has a plurality of terminals, wherein each node in said first storage node set and said set of other nodes is connected to at least one of said terminals, wherein said set of other nodes comprises a first data node for accessing said first storage node set, a first access control node for controlling the access of said first storage node set, and a reference node for said first storage node set, wherein each node in said first storage node set is connected to a port in said first port set, wherein each of said other nodes is connected to one of said other ports, and wherein each of said other ports is connected to one and only one of said other nodes; and   a memory cell comprising a storage node and a second memory base cell, wherein said storage node is the only storage node in said memory cell, wherein said second memory base cell is substantially the same as said first memory base cell, wherein said second memory base cell comprises a second storage node set substantially the same as said first storage node set, and wherein said storage node comprises said second storage node set.   
     
     
         10 . The integrated circuit of  claim 9 , wherein said set of other nodes further comprises a second data node for accessing said first storage node set and a second access control node for controlling the access of said first storage node set. 
     
     
         11 . The integrated circuit of  claim 9 , wherein said plurality of circuit elements comprises a transistor having a body terminal, and wherein said set of other nodes further comprises a body node connected to said body terminal. 
     
     
         12 . The integrated circuit of  claim 9 , further comprising a plurality of other structures each being selected from the group consisting of a probe pad, a bond pad, and a bump, wherein each port in said first port set and said set of other ports is connected to one of said other structures, and wherein each of said other structures is connected to one and only one port in said first port set and said set of other ports. 
     
     
         13 . The integrated circuit of  claim 9 , wherein said first structure further comprises a plurality of other memory base cells and a third port set, wherein said first memory base cell and said plurality of other memory base cells together form an array having substantially the same configuration as a memory array, wherein each of said other memory base cells is substantially the same as said first memory base cell, wherein each of said other memory base cells is adjacent to said first memory base cell, and wherein at least one of the access control nodes in said other memory base cells and nodes in the storage node sets in said other memory base cells is connected to a port in said third port set. 
     
     
         14 . The integrated circuit of  claim 9 , wherein at least two nodes in said first storage node set are connected to a same port in said first port set. 
     
     
         15 . The integrated circuit of  claim 14 , wherein said set of other nodes further comprises a second data node for accessing said first storage node set and a second access control node for controlling the access of said first storage node set. 
     
     
         16 . The integrated circuit of  claim 14 , wherein said plurality of circuit elements comprises a transistor having a body terminal, and wherein said set of other nodes further comprises a body node connected to said body terminal. 
     
     
         17 . The integrated circuit of  claim 14 , further comprising a plurality of other structures each being selected from the group consisting of a probe pad, a bond pad, and a bump, wherein each port in said first port set and said set of other ports is connected to one of said other structures, and wherein each of said other structures is connected to one and only one port in said first port set and said set of other ports. 
     
     
         18 . The integrated circuit of  claim 9 , wherein said first port set consists of one and only one port. 
     
     
         19 . The integrated circuit of  claim 9 , wherein said first structure further comprises a third memory base cell substantially the same as said first memory base cell, wherein each node in said first storage node set and said set of other nodes is connected to the corresponding node in said third memory base cell. 
     
     
         20 . The integrated circuit of  claim 9 , further comprising a second structure selected from the group consisting of on-chip parametric measurement structures and multiplexed structures, wherein said second structure comprises said first structure. 
     
     
         21 . The integrated circuit of  claim 9 , wherein said first memory base cell is substantially the same as said memory cell up through a layer selected from the group consisting of a gate layer, a contact layer, and a metal1 layer. 
     
     
         22 . The integrated circuit of  claim 9 , wherein said first structure is in scribe line.