Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region

Abstract

A field effect transistor (FET) in a semiconductor die including an active region housing active cells, a non-active region with no active cells therein, a drift region of a first conductivity type, a body region of a second conductivity type over the drift region, and a plurality of trenches extending through the body region and into the drift region. Each trench includes a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode. The FET further includes source regions of the first conductivity type in the body region adjacent to each trench, heavy body regions of the second conductivity type in the body regions adjacent the source regions, and a source interconnect layer contacting the source regions and heavy body regions. The shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.

1 - 5 . (canceled) 
     
     
         6 . A field effect transistor (FET) in a semiconductor die comprising:
 an active region housing active cells;   a non-active region with no active cells therein;   a drift region of a first conductivity type;   a body region of a second conductivity type over the drift region;   a plurality of trenches extending through the body region and into the drift region, each trench including a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode;   source regions of the first conductivity type in the body region adjacent to each trench;   heavy body regions of the second conductivity type in the body regions adjacent the source regions; and   a source interconnect layer contacting the source regions and heavy body regions;   wherein the shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.   
     
     
         7 . The FET of  claim 6  wherein the gate electrode is recessed in the trench to below a top surface of the source regions, the FET further comprising a dielectric material over the gate electrode for insulating the gate electrode and the source interconnect layer from one another. 
     
     
         8 . The FET of  claim 6  further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein each trench terminates within the drift region. 
     
     
         9 . The FET of  claim 6  further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein each trench extends through the drift region and terminates within the substrate. 
     
     
         10 . The FET of  claim 6  further comprising an inter-electrode dielectric between the shield electrode and the gate electrode in each trench, wherein the shield electrode is electrically connected to the gate electrode by an additional connection through the inter-electrode dielectric. 
     
     
         11 . The FET of  claim 6  wherein the non-active region includes a gate runner region extending through a middle portion of the die, the shield electrode and gate electrode extending out of each trench and into the gate runner region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer. 
     
     
         12 . The FET of  claim 6  wherein the non-active region includes a termination region extending along a perimeter of the die, the shield electrode and gate electrode extending out of each trench and into the termination region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer.