Latency signal generator and method thereof

Abstract

A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

1 . A latency signal generator, comprising:
 a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals;   a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals; and   a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.   
     
     
         2 . The latency signal generator of  claim 1 , wherein a signal set includes a given adjusted sampling clock signal from among the plurality of adjusted sampling clock signals and a given adjusted latch enable signal from among the plurality of adjusted latch enable signals, and each of the plurality of latency latches selectively latches the given internal read command based on a different signal set. 
     
     
         3 . The latency signal generator of  claim 1 , further comprising:
 a latency controller receiving CAS latency information and outputting a sampling selection control signal and an enable selection control signal corresponding to the CAS latency information;   a transfer control signal generator controlling the outputs of the latency latches based on a plurality of transfer control signals generated from a data output clock signal;   an output control signal generator receiving one of the plurality of transfer control signals, generating a plurality of output control signals, and controlling the outputs of the latency latches in a row unit based on the plurality of output control signals;   an output latch generating a latency signal based on one or more outputs of the plurality of latency latches,   wherein the received clock signal is an internal clock signal and the sampling clock signal generator adjusts the plurality of initial sampling clock signals based on the sampling selection control signal to generate the plurality of adjusted sampling clock signals, and   the latch enable signal supply unit adjusts the plurality of initial latch enable signals based on the enable selection control signal to generate the plurality of adjusted latch enable signals.   
     
     
         4 . The latency signal generator of  claim 3 , wherein the plurality of adjusted sampling clock signals number N, the plurality of adjusted latch enable signals number M, and the plurality of latency latches number (M×N) 
     
     
         5 . The latency signal generator of  claim 3 , wherein the latency controller includes:
 a first plurality of OR gates, each of the first plurality of OR gates receiving the CAS latency information and generating respective bits of the sampling selection control signal; and   a second plurality of OR gates, each of the second plurality of OR gates receiving the CAS latency information and generating respective bits of the enable selection control signal.   
     
     
         6 . The latency signal generator of  claim 4 , wherein the latency controller includes:
 N OR gates, each of the N OR gates including M input terminals and generating respective bits of the sampling selection control signal; and   M OR gates, each of the M OR gates including N input terminals and generating respective bits of the enable selection control signal.   
     
     
         7 . The latency signal generator of  claim 3 , wherein the sampling clock signal generator includes:
 a shift register unit receiving the internal clock signal and generating the plurality of initial sampling clock signals; and   a multiplexer unit adjusting the sequence of the plurality of initial sampling clock signals based on the sampling selection control signal to output the plurality of adjusted sampling clock signals.   
     
     
         8 . The latency signal generator of  claim 7 , wherein the multiplexer unit includes:
 a first multiplexer outputting one of the plurality of initial sampling clock signals as a first adjusted sampling clock signal, in response to the sampling selection control signal.   
     
     
         9 . The latency signal generator of  claim 8 , wherein the multiplexer unit further includes:
 at least one additional multiplexer, each of the at least one additional multiplexer outputting a given initial sampling clock signal from among the plurality of initial sampling clock signals as a corresponding adjusted sampling clock signal of the plurality of adjusted sampling clock signals, in response to the sampling selection control signal.   
     
     
         10 . The latency signal generator of  claim 1 , wherein the latch enable signal supply unit includes:
 a shift register unit receiving the given one initial sampling clock signal and generating the plurality of initial latch enable signals;   a first multiplexer unit adjusting the sequence of the plurality of initial latch enable signals based on the enable selection control signal to generate the plurality of adjusted latch enable signals;   a second multiplexer unit including a plurality of enable multiplexers, each of the plurality of enable multiplexers receiving at least two adjusted latch enable signals from among the plurality of adjusted latch enable signals, and outputting one of the at least two adjusted latch enable signals to a corresponding latency latch; and   a selection controller receiving the sampling selection control signal, generating a plurality of selection signals, outputting the plurality of selection signals to enable multiplexers of a corresponding column, and controlling the enable multiplexers such that the outputted one of the at least two adjusted latch enable signals is output to the corresponding latency latch.   
     
     
         11 . The latency signal generator of  claim 10 , wherein the first multiplexer unit includes:
 a first multiplexer outputting one of the plurality of initial latch enable signals as a first adjusted latch enable signal, in response to the enable selection control signal.   
     
     
         12 . The latency signal generator of  claim 11 , wherein the first multiplexer unit further includes:
 at least one additional multiplexer, each of the at least one additional multiplexer outputting a given initial latch enable signal from among the plurality of initial latch enable signals as a corresponding adjusted latch enable signal of the plurality of adjusted latch enable signals, in response to the enable selection control signal.   
     
     
         13 . The latency signal generator of  claim 10 , wherein the selection controller includes:
 a first OR gate receiving a first bit of the sampling selection control signal through a first input terminal of the first OR gate and outputting a first selection signal of the plurality of selection signals to enable multiplexers of a first column.   
     
     
         14 . The latency signal generator of  claim 13 , wherein the selection controller further includes:
 at least one additional OR gate receiving at least one additional bit of the sampling selection control signal through a first input terminal of the at least one additional OR gate and outputting at least one additional selection signal of the plurality of selection signals to enable multiplexers of at least one additional column,   and wherein a second input terminal of a given OR gate is connected to an output terminal of another given OR gate, and   a second input terminal of the last one additional OR gate is connected to a ground voltage.   
     
     
         15 . The latency signal generator of  claim 1 , wherein each of the plurality of latency latches latches the given internal read command, in response to a rising edge of a given adjusted sampling clock signal received while a given adjusted latch enable signal received is set to a given logic level. 
     
     
         16 . The latency signal generator of  claim 3 , wherein the transfer control signal generator includes:
 a shift register unit receiving the data output clock signal and generating the plurality of transfer control signals; and   a plurality of transfer switches controlling the outputs of the plurality of latency latches in a column unit, in response to the plurality of transfer control signals.   
     
     
         17 . The latency signal generator of  claim 3 , wherein the received one of the plurality of transfer control signals at the output control signal generator is a first of the plurality of transfer control signals. 
     
     
         18 . The latency signal generator of  claim 17 , wherein the output control signal generator includes:
 a shift register unit receiving the first transfer control signal and generating the plurality of output control signals; and   an output switch unit including a first transfer switch controlling the outputs of latency latches of a first row, in response to a first output control signal of the plurality of output control signals, and at least one additional transfer switch controlling the outputs of latency latches of at least one additional row, in response to at least one additional output control signal of the plurality of output control signals.   
     
     
         19 . The latency signal generator of  claim 3 , wherein the CAS latency information is transmitted from a mode register to the latency controller. 
     
     
         20 . The latency signal generator of  claim 3 , wherein the data output clock signal is a clock signal generated from an external clock signal by a delay locked loop (DLL).