Advanced processor scheduling in a multithreaded system

Abstract

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

1 - 19 . (canceled) 
     
     
         20 . A processing system, comprising:
 at least one processor to execute multiple threads, in which the at least one processor is coupled to a scheduler to receive packet segments for processing;   the scheduler is to receive a plurality of the packet segments having an ordering, wherein a subsequent packet segment in the ordering corresponds to either (a) a next positional packet thread if the next positional packet thread contains an available packet segment or (b) a subsequent packet thread having an available packet segment.