Pixel layout structure for raising capability of detecting amorphous silicon residue defects and method for manufacturing the same

Abstract

Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.

1 . A method of manufacturing a pixel layout structure capable of increasing the capability of detecting amorphous silicon residue defects, comprising:
 providing a transparent substrate;   forming a first metal layer on said transparent substrate, and etching said first metal layer to form a pattern of a gate line, a gate electrode of a transistor, and at least a shadow layer;   forming a first insulation layer on said first metal layer;   forming an a-Si layer on said first insulation layer, and etching said a-Si layer to form a channel of said transistor and at least a dummy layer, wherein said dummy layer is disposed above said shadow layer;   forming a second metal layer on said a-Si layer, and etching said second metal layer to form a data line and a source electrode and a drain electrode of said transistor;   forming a second insulation layer on said second metal layer, and etching said second insulation layer to form a plurality of through holes; and   forming a transparent conductive layer on said second insulation layer, whereby said drain electrode of said transistor is electronically connected with said transparent conductive layer by means of said through holes.   
     
     
         2 . The method as claimed in  claim 1 , wherein said transparent substrate is a glass substrate. 
     
     
         3 . The method as claimed in  claim 1 , wherein said transistor is a thin film transistor. 
     
     
         4 . The method as claimed in  claim 1 , wherein said dummy layer further includes two strips, each of said strips is respectively disposed on said first insulation layer which is located at a lateral side of said data line, and under each of said dummy layers is correspondingly provided with said shadow layer. 
     
     
         5 . The method as claimed in  claim 1 , wherein said first insulation layer is made of dielectric materials of silicon oxide or silicon nitride. 
     
     
         6 . The method as claimed in  claim 1 , wherein said second insulation layer is made of dielectric materials of silicon oxide or silicon nitride. 
     
     
         7 . The method as claimed in  claim 1 , wherein said etching step is realized through wet etching or dry etching. 
     
     
         8 . The method as claimed in  claim 1 , wherein said second metal layer as well as said second insulation layer and said transparent conductive layer together form an electrode structure, and said electrode structure is a storage-capacitor-utilizing-common-wiring (Cs on Com) structure or a storage-capacitor-utilizing-gate-wiring (Cs on Gate) structure. 
     
     
         9 . The method as claimed in  claim 8 , wherein in case that said electrode structure is said storage-capacitor-utilizing-common-wiring (Cs on Com) structure, said electrode structure has a layout design which is chosen from a metal layer-insulation layer-ITO layer (MII) electrode structure, a metal layer-insulation layer-semiconductor layer (MIS) electrode structure, and a metal layer-insulation layer-metal layer (MIM) electrode structure.