FET with FUSI Gate and Reduced Source/Drain Contact Resistance

Abstract

A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

1 . A method for forming a field effect transistor (FET), the method comprising:
 forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer;   forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer;   implanting the gate silicide and the source/drain silicide with dopants; and   performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming highly doped source/drain regions in the silicon layer; and   forming the source/drain silicide regions in the highly doped source/drain regions.   
     
     
         3 . The method of  claim 1 , wherein simultaneously forming gate silicide from the polysilicon layer and forming source/drain silicide regions in the silicon layer comprises:
 depositing a metal layer over the gate polysilicon and the silicon layer;   annealing the metal layer, the gate polysilicon, and the silicon layer such that the metal layer reacts with the gate polysilicon to form the gate silicide and reacts with a portion of the silicon layer to form the source/drain silicide regions; and   in the event a portion of the metal layer does not react with the gate polysilicon or the silicon layer, removing the unreacted portion of the metal layer.   
     
     
         4 . The method of  claim 3 , wherein the deposited metal comprises one of nickel (Ni) and nickel platinum (NiPt) 
     
     
         5 . The method of  claim 4 , wherein the deposited metal comprises Ni, and a ratio of a thickness of the gate polysilicon to a thickness of the deposited metal layer is about 1.8 or less. 
     
     
         6 . The method of  claim 1 , wherein the gate interfacial layer is configured to determine a workfunction of the gate stack, and wherein the source/drain interfacial layers are configured to determine a contact resistance of the source/drain silicide regions. 
     
     
         7 . The method of  claim 1 , wherein the gate silicide and the source/drain silicide regions have approximately the same thickness. 
     
     
         8 . The method of  claim 1 , wherein the FET comprises an nFET, and the dopants comprise at least one of arsenic and phosphorous. 
     
     
         9 . The method of  claim 1 , wherein the FET comprises a pFET, and the dopants comprise one at least one of boron, indium, and aluminum. 
     
     
         10 . The method of  claim 1 , wherein forming the FET gate stack further comprises forming a sacrificial layer over the gate polysilicon, and forming at least one nitride spacer adjacent to the gate stack after formation of the FET gate stack. 
     
     
         11 . The method of  claim 11 , further comprising removing the sacrificial layer after formation of the at least one nitride spacer. 
     
     
         12 . The method of  claim 12 , wherein the sacrificial layer comprises silicon germanium, and removing the sacrificial layer comprises a wet etch of H 2 O:NH 4 OH:H 2 O 2 =5:1:1 solution at 85° C. 
     
     
         13 . The method of  claim 1 , wherein the silicon layer comprises extremely thin silicon on insulator (ETSOI), and wherein the FET comprises a Schottky source/drain FET. 
     
     
         14 . A field effect transistor (FET), comprising:
 source/drain silicide regions located in a silicon layer;   source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and   a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.   
     
     
         15 . The FET of  claim 14 , further comprising highly doped source/drain regions located in the silicon layer, wherein the source/drain silicide regions are located in the highly doped source/drain regions, and the source/drain interfacial layers are located in between the source/drain silicide regions and the highly doped source/drain regions. 
     
     
         16 . The FET of  claim 14 , wherein the source/drain silicide regions and the gate silicide comprise one of NiSi and NiPtSi. 
     
     
         17 . The FET of  claim 14 , wherein the source/drain silicide regions and the gate silicide have approximately the same thickness. 
     
     
         18 . The FET of  claim 14 , wherein the gate interfacial layer is configured to determine a workfunction of the gate stack, and wherein the source/drain interfacial layers are configured to determine a contact resistance of the source/drain silicide regions. 
     
     
         19 . The FET of  claim 14 , wherein the silicon layer comprises extremely thin silicon on insulator (ETSOI), and wherein the FET comprises a Schottky source/drain FET.