Charge Balance Techniques for Power Devices

Abstract

A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.

1 - 18 . (canceled) 
     
     
         19 . A silicon wafer comprising:
 a silicon region of first conductivity type; and   a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.   
     
     
         20 . The silicon wafer of  claim 19  wherein the first conductivity type is n type and second conductivity type is p type. 
     
     
         21 . A silicon die comprising:
 a silicon region of first conductivity type; and   a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.   
     
     
         22 . The silicon wafer of  claim 21  wherein the first conductivity type is n type and second conductivity type is p type. 
     
     
         23 . A method of forming a charge balance structure in a semiconductor die having a silicon region of first conductivity type, the method comprising:
 forming a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.   
     
     
         24 . The silicon wafer of  claim 23  wherein the forming step comprises:
 forming a plurality of trenches extending to the predetermined depth in the silicon region, the trenches extending from the one edge of the silicon die to the opposing edge of the silicon die; and 
 filling the plurality of trenches with silicon material of the second conductivity type. 
 
     
     
         25 . The method of  claim 23  wherein the first conductivity type is n type and second conductivity type is p type.