US2011250726A1PendingUtilityA1

Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof

Assignee: PANASONIC CORPPriority: Jun 4, 2007Filed: Jun 22, 2011Published: Oct 13, 2011
Est. expiryJun 4, 2027(~0.9 yrs left)· nominal 20-yr term from priority
H10D 84/0109H10D 84/038H10D 84/401H10D 84/05H10D 84/01
44
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Claims

Abstract

Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer.

Claims

exact text as granted — not AI-modified
1 . A method for manufacturing a semiconductor device, comprising:
 forming a channel layer by epitaxially growing a semiconductor layer in which an ion species of a first conductivity is implanted on a semiconductor substrate;   implanting the ion species of the first conductivity in the semiconductor substrate;   forming a source region, a drain region, and an emitter region which are of the first conductivity, by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted; and   sequentially and epitaxially growing, on the channel layer, an emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer.   
     
     
         2 . The method for manufacturing the semiconductor device according to  claim 1 ,
 wherein in forming a channel layer, an InGaAs layer in which a δ doped layer is formed is epitaxially grown,   in implanting, a silicon (Si) ion, a tellurium (Te) ion, or a selenium (Se) ion is implanted into the semiconductor substrate,   in sequentially and epitaxially growing, an emitter layer made of an n-type InGaP, a base layer made of a p-type GaAs, an n-type collector layer or a non-doped collector layer, and an n-type sub-collector layer with an impurity concentration higher than an impurity concentration of the collector layer are sequentially and epitaxially grown, and   the method for manufacturing the semiconductor device further comprises:   exposing a surface of the base layer and a surface of the emitter layer by removing a part of the collector layer, a part of the sub-collector layer, and a part of the base layer;   forming a source electrode contacting the source region, a drain electrode contacting the drain region, and an emitter electrode contacting the emitter region; and   forming a base electrode contacting the base layer and a gate electrode on a portion positioned between the source region and the drain region in the emitter layer.   
     
     
         3 . The method for manufacturing the semiconductor device according to  claim 2 ,
 wherein in forming the source electrode, the drain electrode, and the emitter electrode, after forming an AuGe/Au-based metal on the emitter layer, the emitter electrode, the source electrode, and the drain electrode are formed at the same time by thermally diffusing the AuGe/Au-based metal from a top of the emitter layer so that the AuGe/Au-based metal ohmically contacts the emitter region, the source region, and the drain region.   
     
     
         4 . The method for manufacturing the semiconductor device according to  claim 2 ,
 wherein in forming the base electrode and the gate electrode, the base electrode and the gate electrode, which are made of a single layer film or a laminated film, are formed at the same time, the film including Pt.   
     
     
         5 . The method for manufacturing the semiconductor device according to  claim 2 ,
 wherein in exposing, a part of the base layer is removed such that a portion positioned between the source region and the drain region in the base layer remains, and   in said forming of the base electrode and the gate electrode, a gate electrode made of a single layer film or a laminated film is formed on the base layer positioned between the source region and the drain region, the film including Pt.

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