US2011253439A1PendingUtilityA1

Circuit substrate and manufacturing method thereof

Assignee: SUBTRON TECHNOLOGY CO LTDPriority: Apr 20, 2010Filed: Jun 18, 2010Published: Oct 20, 2011
Est. expiryApr 20, 2030(~3.8 yrs left)· nominal 20-yr term from priority
Inventors:Tzu-Wei Huang
B32B 38/04B32B 2311/00B32B 2457/00H05K 3/02H05K 3/0052H05K 3/462H05K 3/427H05K 3/46Y10T29/49126Y10T29/49165H05K 2201/09563B32B 37/02Y10T29/49155H05K 3/421B32B 2038/047H05K 2203/1536B32B 38/10B23K 2101/42B32B 2307/202H05K 3/0097H05K 2201/09527B32B 2311/12B32B 37/0084H05K 2201/09509Y10T29/49156H05K 2203/1572H05K 3/4652B32B 2307/206B32B 37/04B32B 2457/08H05K 1/115H05K 3/423H05K 3/4682H05K 2201/09918B23K 11/11
57
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

Claims

exact text as granted — not AI-modified
1 . A method for manufacturing a circuit substrate, comprising:
 bonding peripheries of two metal layers to form a sealed area;   forming two insulating layers on the two metal layers;   forming two conductive layers on the two insulating layers;   laminating the two insulating layers and the two conductive layers and the two metal layers being embedded between the two insulating layers;   removing a part of the two insulating layers and a part of the two conductive layers to form a plurality of blind holes exposing the two metal layers;   forming a conductive material in the blind holes and on remained portions of the two conductive layer; and   separating the sealed area of the two metal layer to form two separated circuit substrates.   
     
     
         2 . The method for manufacturing a circuit substrate of  claim 1 , wherein the method for bonding the peripheries of the two metal layers comprises an electric welding process or a spot-welding process. 
     
     
         3 . The method for manufacturing a circuit substrate of  claim 1 , wherein after bonding the peripheries of the two metal layers, the method further comprises forming at least a through hole passing through the sealed area and the two insulating layer further fill in the through hole when the two insulating layers are laminated. 
     
     
         4 . The method for manufacturing a circuit substrate of  claim 1 , wherein the method for forming the conductive material comprises an electroplating process. 
     
     
         5 . The method for manufacturing a circuit substrate of  claim 1 , wherein after separating the sealed area of the two metal layers, the method further comprises patterning the conductive material and the two conductive layers. 
     
     
         6 . A method for manufacturing a circuit substrate, comprising:
 bonding peripheries of two metal layers to form a sealed area;   forming two insulating layers on the two metal layers and forming two inner conductive layers on the two insulating layers;   laminating the two insulating layers and the two inner conductive layers and the two metal layers bonded with each other being embedded in the two insulating layers;   patterning the two inner conductive layers, forming another two insulating layers on the two inner conductive layers, and forming two outer conductive layers on the another two insulating layers;   laminating the insulating layers and the two outer conductive layers and the two inner conductive layers being embedded in the insulating layers; and   separating the sealed area of the two metal layers to form two separated circuit substrates.   
     
     
         7 . The method for manufacturing a circuit substrate of  claim 6 , wherein the method for bonding the peripheries of the two metal layers comprises an electric welding process or a spot-welding process. 
     
     
         8 . The method for manufacturing a circuit substrate of  claim 6 , wherein after bonding the peripheries of the two metal layers, the method further comprises forming at least a through hole passing through the sealed area and the two insulating layers further fill in the through hole when the two insulating layers are laminated. 
     
     
         9 . The method for manufacturing a circuit substrate of  claim 6 , wherein after separating the sealed area of the two metal layers, the method further comprises:
 removing a part of the insulating layers, a part of the metal layer, and a part of the outer conductive layer to form a plurality of blind holes exposing the inner conductive layer; and   forming a conductive material in the blind holes and on remained portions of the metal layer and the outer conductive layer.   
     
     
         10 . The method for manufacturing a circuit substrate of  claim 9 , wherein after forming the conductive material, the method further comprises patterning the conductive material, the metal layer, and the outer conductive layer. 
     
     
         11 . A circuit substrate formed by the method of  claim 6 , the circuit substrate comprising:
 a metal layer;   an outer conductive layer;   an inner conductive layer located between the metal layer and the outer conductive layer; and   two insulating layers respectively located between the metal layer and the inner conductive layer and between the outer conductive layer and the inner conductive layer.   
     
     
         12 . The circuit substrate of  claim 11 , further comprising a conductive material located in a plurality of blind holes passing through the insulating layers and the conductive material being electrically connected between the metal layer and the inner conductive layer and between the outer conductive layer and the inner conductive layer.

Join the waitlist — get patent alerts

Track US2011253439A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.