Transparent nanowire transistors and methods for fabricating same

Abstract

Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.

1 . A nanowire transistor device comprising:
 one or more semiconducting nanowires extending between a source electrode and a drain electrode, and   a gate dielectric in contact with the one or more nanowires,   wherein each of the gate dielectric, the source electrode and the drain electrode is transparent.   
     
     
         2 . The device of  claim 1 , wherein the one or more semiconducting nanowires comprise one or more elements selected from Group, 12, Group 13, Group 14, Group 15, and Group 16. 
     
     
         3 . The device of  claim 2 , wherein the one or more semiconducting nanowires are selected from p-type Ge nanowires and n-type Ge nanowires. 
     
     
         4 . The device of  claim 1 , wherein the one or more semiconducting nanowires comprise a transparent metal oxide. 
     
     
         5 . The device of  claim 4 , wherein the one or more metal oxide nanowires are selected from ZnO nanowires, In 2 O 3  nanowires, and SnO 2  nanowires. 
     
     
         6 . The device of  claim 1 , wherein the nanowire transistor comprises a single semiconducting nanowire. 
     
     
         7 . The device of  claim 1 , wherein the nanowire transistor comprises a plurality of semiconducting nanowires. 
     
     
         8 . The device of  claim 1 , wherein the gate dielectric comprises one or more transparent metal oxides. 
     
     
         9 . The device of  claim 1 , wherein the gate dielectric comprises a multi-layer composition, the multi-layer composition comprising periodically alternating layers, wherein the alternating layers comprise one or more layers comprising a polarizable moiety, and one or more layers comprising a silyl or siloxane moiety. 
     
     
         10 . The device of  claim 9 , wherein the polarizable moiety comprises a stilbazonium group. 
     
     
         11 . The device of  claim 9 , wherein at least some of the alternating layers are coupled to an adjacent layer by a coupling layer comprising a siloxane matrix. 
     
     
         12 . The device of  claim 11 , wherein at least some of the alternating layers are coupled to one another or the siloxane matrix via a condensation reaction. 
     
     
         13 . The device of  claim 9 , wherein at least some of the alternating layers comprise a condensation product of a silane-substituted stilbazolium compound and a trisiloxane compound. 
     
     
         14 . The device of  claim 9 , wherein the alternating layers comprise one or more layers comprising a sigma moiety. 
     
     
         15 . The device of  claim 14 , wherein at least some of the alternating layers comprise a condensation product of a bis(silyl)-C 4 - about C 10  alkyl compound and a trisiloxane compound. 
     
     
         16 . The device of  claim 1 , wherein the gate dielectric comprises a crosslinked polymeric material. 
     
     
         17 . The device of  claim 1 , wherein each of the source electrode and the drain electrode independently comprises indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, zinc indium tin oxide, fluorinated tin oxide, gallium zinc oxide, gallium indium oxide, or gallium indium tin oxide. 
     
     
         18 . The device of  claim 1  comprising a transparent gate electrode defined under the gate dielectric. 
     
     
         19 . The device of  claim 18 , wherein the transparent gate electrode comprises indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, zinc indium tin oxide, fluorinated tin oxide, gallium zinc oxide, gallium indium oxide, or gallium indium tin oxide. 
     
     
         20 . The device of  claim 1 , wherein the gate dielectric is deposited on a transparent substrate. 
     
     
         21 . The device of  claim 20 , wherein the transparent substrate is glass or plastic. 
     
     
         22 . An array comprising a device of  claim 1 . 
     
     
         23 . An electronic circuit comprising the array of  claim 22 . 
     
     
         24 . A method of fabricating a nanowire transistor device, the method comprising:
 applying a gate electrode layer on a substrate;   applying a dielectric layer on the gate electrode layer;   applying one or more semiconducting nanowires on the dielectric layer; and   applying a source electrode and a drain electrode on the dielectric layer;   wherein the application of the gate electrode layer, the application of the dielectric layer, the application of the one or more semiconducting nanowires, and the application of the source electrode and the drain electrode are conducted at a temperature less than about 100° C., and   wherein each of the gate electrode layer, the dielectric layer, the source electrode, the drain electrode, and the substrate is transparent, and the one or more semiconducting nanowires extend between the source electrode and the drain electrode.   
     
     
         25 . The method of  claim 24 , wherein the application of the dielectric layer comprises forming at least one condensation product of a silane-substituted stilbazoium compound and a trisiloxane compound, and optionally, at least one condensation product of a bis(silyl)-C 4 - about C 10  alkyl compound and a trisiloxane compound. 
     
     
         26 . The method of  claim 24 , wherein the application of the one or more semiconducting nanowires comprises dispersing a suspension comprising one or more semiconducting nanowires on the dielectric layer. 
     
     
         27 . The method of  claim 24  comprising subjecting the nanowire transistor device to ozone treatment.