Advanced processor with mechanism for fast packet queuing operations

Abstract

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

1 - 30 . (canceled) 
     
     
         31 . A processor, comprising:
 a packet processing system to execute a plurality of threads to process packets;   a packet distribution engine to: receive a plurality of packets in a first order; assign packet descriptors to respective packets of said plurality of packets, the packet descriptors comprising respective sequence numbers; provide the respective packets to memory; and distribute the packet descriptors to threads of the packet processing system without moving the respective packets from memory; and   a packet ordering device to receive the packet descriptors from the packet processing system in a second order different from the first order and to establish an order for distributing the respective packets based, at least in part, upon the respective sequence numbers of the packet descriptors.   
     
     
         32 . The processor of  claim 31 , further comprising an interface coupled to the packet distribution engine and selected from the group consisting of an XGMII interface, an SPI-4.2 interface and an RGMII interface. 
     
     
         33 . The processor of  claim 31 , wherein the packet distribution engine is configured to receive the plurality of packets in the first order from a networking input. 
     
     
         34 . The processor of  claim 33 , further comprising at least two interfaces coupled to the packet distribution engine and selected from the group consisting of an RGMII interface, an XGMII interface, and an SPI-4.2 interface. 
     
     
         35 . The processor of  claim 31 , wherein the packet distribution engine is separate from said packet ordering device. 
     
     
         36 . The processor of  claim 31 , wherein the packet processing system comprises a plurality of processor cores, a respective processor core for executing multiple threads. 
     
     
         37 . The processor of  claim 31 , wherein the packet processing system comprises a plurality of processor cores, each processor core for supporting a plurality of operating systems. 
     
     
         38 . The processor of  claim 31 , wherein the order for distributing the respective packets is the same as the first order. 
     
     
         39 . The processor of  claim 31 , wherein the packet ordering device is configured to drop a packet descriptor after a time-out counter expires such that the order established by the packet ordering device for distributing the respective packets does not include the packet associated with the dropped packet descriptor, and the next packet descriptor in the first order replaces the dropped packet descriptor. 
     
     
         40 . The processor of  claim 31 , wherein the packet ordering device is configured to distribute the respective packets to a networking output in the order established by the packet ordering device. 
     
     
         41 . A method of controlling a flow of packets, the method comprising:
 receiving a plurality of packets in a first order;   storing respective packets of said plurality of packets in memory;   assigning, by a packet distribution engine, packet descriptors including respective sequence numbers to the respective packets of said plurality of packets;   distributing, by said packet distribution engine, said packet descriptors to threads of a packet processing system, without moving the respective packets from the memory;   receiving, at a packet ordering device, the packet descriptors from the packet processing system in a second order different from the first order; and   establishing, by said packet ordering device, an output order for distributing the respective packets based, at least in part, upon the respective sequence numbers of the packet descriptors.   
     
     
         42 . The method of  claim 41 , wherein said output order is the same as said first order. 
     
     
         43 . The method of  claim 41 , wherein said output order is the same as said first order except that a non-arriving packet descriptor is dropped after a time-out counter has expired. 
     
     
         44 . The method of  claim 41 , further comprising:
 dropping a packet descriptor after a time-out counter expires such that the output order does not include the packet associated with the dropped packet descriptor, and the next packet descriptor in the first order replaces the dropped packet descriptor.   
     
     
         45 . The method of  claim 41 , further comprising distributing the respective packets in the output order via an interface selected from the group consisting of an XGMII interface, an SPI-4.2 interface and an RGMII interface. 
     
     
         46 . The method of  claim 41 , wherein the packet processing system comprises a plurality of processor cores, each processor core executing multiple threads. 
     
     
         47 . The method of  claim 41 , wherein the packet processing system comprises a plurality of processor cores, and each processor core supports a plurality of operating systems. 
     
     
         48 . The method of  claim 41 , wherein the packet ordering device distributes the respective packets to a networking output in the output order.