Ball grid array stack

Abstract

The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and . interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

1 . A method comprising:
 providing a first layer that includes opposing major surfaces, a first layer lateral surface, a first layer conductive trace, and an electronic component disposed on at least one of the opposing major surfaces, wherein the first layer conductive trace terminates on the first layer lateral surface to define a first layer access lead;   providing a second layer that includes an electronic component, a second layer lateral surface, and a second layer conductive trace, wherein the second layer conductive trace terminates on the second layer lateral surface to define a second layer access lead;   after provision of the first and second layers, bonding the first and second layers with an interposer such that the interposer is disposed between the first and second layers, wherein the interposer includes an interposer lateral surface, and wherein the first layer lateral surface, the interposer lateral surface, and the second layer lateral surface define a substantially coplanar package lateral surface; and   disposing a conductive layer interconnect trace on the substantially coplanar package lateral surface to electrically connect the first layer access lead and the second layer access lead.   
     
     
         2 . The method of  claim 1 , wherein the first layer further comprises an opposite lateral surface on an opposite side of the first layer as the first layer lateral surface, and wherein at least one of the opposing major surfaces extends from the first layer lateral surface to the opposite lateral surface. 
     
     
         3 . The method of  claim 1 , wherein each of the opposing major surfaces includes an electronic component disposed thereon. 
     
     
         4 . The method of  claim 1 , wherein the interposer is formed separately from the first and second layers. 
     
     
         5 . The method of  claim 1 , wherein the interposer further comprises a frame having an aperture defined therein, and wherein the aperture is configured to receive at least one of the electronic components from the first or second layers. 
     
     
         6 . The method of  claim 5 , wherein after said bonding the first and second layers with an interposer, an unfilled gap exists in the aperture between the interposer and at least one of the electronic component of the first layer or the electronic component of the second layer. 
     
     
         7 . The method of  claim 1 , wherein said disposing a conductive layer interconnect trace comprises:
 metallizing the substantially coplanar package lateral surface with a metallization; and   delineating the metallization to form one or more trenches.   
     
     
         8 . The method of  claim 1 , wherein the interposer further comprises at least one of a dielectric material or an insulative organic material. 
     
     
         9 . The method of  claim 1 , further comprising modifying the first layer lateral surface and the second layer lateral surface to define the substantially coplanar package lateral surface. 
     
     
         10 . The method of  claim 9 , wherein said modifying comprises lapping, grinding, or saw-cutting the first layer lateral surface and the second layer lateral surface. 
     
     
         11 . The method of  claim 1 , wherein the electronic component of the first layer comprises a prepackaged integrated circuit chip. 
     
     
         12 . The method of  claim 11 , wherein the prepackaged integrated circuit chip comprises a ball grid array package. 
     
     
         13 . The method of  claim 11 , wherein the prepackaged integrated circuit chip comprises a thin small outline package. 
     
     
         14 . The method of  claim 11 , further comprising forming an electrical connection between the prepackaged integrated circuit chip and the first layer conductive trace. 
     
     
         15 . The method of  claim 14 , wherein the electrical connection comprises a flip-chip bond or a wire bond. 
     
     
         16 . The method of  claim 14 , wherein the electrical connection comprises an electrically-conductive epoxy. 
     
     
         17 . The method of  claim 1 , wherein said disposing a conductive layer interconnect trace on the substantially coplanar package lateral surface comprises forming an electrically-conductive T-connection between the conductive layer interconnect, the first layer access lead, and the second layer access lead. 
     
     
         18 . The method of  claim 1 , wherein said bonding the first and second layers with an interposer comprises bonding the first and second layers and the interposer with an adhesive. 
     
     
         19 . A method comprising:
 providing a first layer that includes opposing major surfaces, a first layer lateral surface, a first layer conductive trace, and an electronic component disposed on at least one of the opposing major surfaces, wherein the first layer conductive trace terminates on the first layer lateral surface to define a first layer access lead;   providing a second layer that includes a second layer lateral surface and a second layer conductive trace, wherein the second layer conductive trace terminates on the second layer lateral surface to define a second layer access lead;   after provision of the first and second layers, bonding the first and second layers with an interposer such that the interposer is disposed between the first and second layers, wherein the interposer includes an interposer lateral surface and a frame defining an aperture, wherein said bonding the first and second layers with an interposer comprises positioning the electronic component within the aperture, wherein the aperture includes an unfilled gap between the electronic component and the frame of the interposer, and wherein the first layer lateral surface, the interposer lateral surface, and the second layer lateral surface define a package lateral surface; and   disposing a conductive layer interconnect trace on the package lateral surface to electrically connect the first layer access lead and the second layer access lead.   
     
     
         20 . The method of  claim 19 , wherein the first layer further comprises an opposite lateral surface on an opposite side of the first layer as the first layer lateral surface, and wherein at least one of the opposing major surfaces extends from the first layer lateral surface to the opposite lateral surface. 
     
     
         21 . The method of  claim 19 , wherein the interposer is formed separately from the first and second layers. 
     
     
         22 . The method of  claim 19 , wherein said disposing a conductive layer interconnect trace comprises:
 metallizing substantially the entire package lateral surface with a metallization; and   delineating the metallization to form one or more trenches.   
     
     
         23 . The method of  claim 19 , further comprising modifying the first layer lateral surface and the second layer lateral surface to define the package lateral surface, wherein the package lateral surface is substantially coplanar. 
     
     
         24 . The method of  claim 19 , wherein the electronic component of the first layer comprises a ball grid array package or a thin small outline package. 
     
     
         25 . The method of  claim 19 , wherein said disposing a conductive layer interconnect trace on the package lateral surface comprises forming an electrically-conductive T-connection between the conductive layer interconnect, the first layer access lead, and the second layer access lead.