Tri layer metal oxide rewritable non volatile two terminal memory element

Abstract

A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

1 . A re-writable non-volatile two-terminal memory device, comprising:
 a re-writable non-volatile memory element having exactly two terminals consisting of a first terminal and a second terminal, the memory element including directly electrically in series with the first and second terminals
 a first conductive metal oxide (CMO) layer electrically coupled with the first terminal and including first mobile ions having a first polarity, 
 a second CMO layer electrically coupled with the second terminal and including second mobile ions having a second polarity that is opposite the first polarity and the second mobile ions are a different ion type than the first mobile ions, and 
 an insulating metal oxide (IMO) layer positioned between and in direct contact with the first and second CMO layers, the IMO layer having a first thickness that is approximately 50 Å or less and configured for electron tunneling between the first and second CMO layers during read and write operations, and the IMO layer is permeable to the first and second mobile ions only during the write operations. 
   
     
     
         2 . The memory device of  claim 1 , wherein the memory element stores at least one-bit of data as a plurality of conductivity profiles that are retained in the absence of electrical power. 
     
     
         3 . The memory device of  claim 2 , wherein the plurality of conductivity profiles are non-destructively determined by applying a read voltage across the first and second terminals. 
     
     
         4 . The memory device of  claim 2 , wherein the plurality of conductivity profiles are reversibly written by applying a write voltage across the first and second terminals. 
     
     
         5 . The memory device of  claim 1 , wherein the first CMO layer is in direct contact with the first terminal. 
     
     
         6 . The memory device of  claim 1 , wherein the second CMO layer is in direct contact with the second terminal. 
     
     
         7 . The memory device of  claim 1 , wherein the first mobile ions have a first ion mobility and the second mobile ions have a second ion mobility that is different than the first ion mobility. 
     
     
         8 . The memory device of  claim 1  and further comprising:
 a low conductivity region having a second thickness that is substantially less than the first thickness, the first thickness and the second thickness cumulatively form a variable tunnel barrier thickness that is approximately 50 Å or less, the low conductivity region including accumulated mobile ions, the low conductivity region positioned either in the first CMO layer and immediately adjacent to the IMO layer or in the second CMO layer and immediately adjacent to the IMO layer, and 
 the memory element stores non-volatile data as a programmed conductivity when the variable tunnel barrier thickness comprises the first thickness and the second thickness. 
 
     
     
         9 . The memory device of  claim 1 , wherein the first mobile ions comprise oxygen ions and the second mobile ions comprise metal ions. 
     
     
         10 . The memory device of  claim 9 , wherein the first polarity is negative and the second polarity is positive. 
     
     
         11 . The memory device of  claim 1 , wherein the first thickness of the IMO layer is approximately 30 Å or less. 
     
     
         12 . The memory device of  claim 1 , wherein the first CMO layer and the second CMO layer are made from different CMO materials. 
     
     
         13 . The memory device of  claim 12 , wherein the different CMO materials comprise different perovskite materials. 
     
     
         14 . The memory device of  claim 1 , wherein the second CMO layer comprises a non-oxidized form of IMO layer. 
     
     
         15 . The memory device of  claim 1 , wherein the first thickness of the IMO layer is operative to define a variable tunnel barrier thickness and the memory element stores data as an erased conductivity when the variable tunnel barrier thickness comprises the first thickness. 
     
     
         16 . The memory device of  claim 1  and further comprising:
 a non-ohmic device including at least two-terminals and electrically in series with the first and second terminals of the memory element. 
 
     
     
         17 . The memory device of  claim 1 , wherein the first terminal, the second terminal, or both comprises an electrode made from at least one layer of an electrically conductive material. 
     
     
         18 . The memory device of  claim 17 , wherein the at least one layer of the electrically conductive material comprises a metal oxide. 
     
     
         19 . A re-writeable non-volatile memory device, comprising:
 at least one layer of memory, each layer of memory including
 at least one two-terminal cross-point array, each cross-point array including a plurality of first conductive array lines, a plurality of second conductive array lines, and a plurality of memory elements having exactly two-terminals and configured with a first terminal of each memory element electrically coupled with only one of the plurality of first conductive array lines and a second terminal of each memory element electrically coupled with only one of the plurality of second conductive array lines, each memory element is positioned between a cross-point of its respective first and second conductive array lines, each memory element configured to store at least one-bit of non-volatile data as a programmed conductivity or an erased conductivity, and each memory element including electrically in series with its first and second terminals, 
 a first conductive metal oxide (CMO) layer electrically coupled with the first terminal and including first mobile ions having a first polarity, 
 a second CMO layer electrically coupled with the second terminal and including second mobile ions having a second polarity that is opposite the first polarity and the second mobile ions are a different ion type than the first mobile ions, and 
 an insulating metal oxide (IMO) layer positioned between and in direct contact with the first and second CMO layers, the IMO layer having a first thickness that is approximately 50 Å or less and configured for electron tunneling between the first and second CMO layers during read and write operations, and the IMO layer is permeable to the first and second mobile ions only during the write operations. 
   
     
     
         20 . The memory device of  claim 19  and further comprising:
 a low conductivity region having a second thickness that is less than the first thickness, the low conductivity region is present in the memory element only when the memory element stores data as the programmed conductivity, the low conductivity region comprised of accumulated mobile ions, the first thickness and second thickness cumulatively form a variable tunnel barrier thickness that is approximately 50 Å or less, the low conductivity region is positioned either in the first CMO layer adjacent to an interface between the first CMO layer and the IMO layer or in the second CMO layer adjacent to an interface between the second CMO layer and the IMO layer, 
 each memory element stores the non-volatile data as the programmed conductivity when the variable tunnel barrier thickness comprises the first thickness and second thickness, and 
 each memory element stores the non-volatile data as the erased conductivity when the variable tunnel barrier thickness comprises only the first thickness. 
 
     
     
         21 . The memory device of  claim 19  and further comprising:
 a semiconductor substrate including active circuitry fabricated on the semiconductor substrate, at least a portion of the active circuitry is electrically coupled with the plurality of first and second conductive array lines and operative to apply voltages across selected conductive array lines during read and write operations, the at least one layer of memory is in contact with and is fabricated directly over the semiconductor substrate.