Semiconductor device and manufacturing method thereof

Abstract

The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n + -type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT 2 electrically coupled to the n + -type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT 2 formed adjacent to each other in the first direction.

1 . A semiconductor device, comprising:
 a semiconductor substrate with an SOI structure including a support substrate, an insulating layer formed over the support substrate, and a semiconductor layer formed over the insulating layer;   a plurality of field-effect transistors of a first conduction type formed over a main surface of the semiconductor substrate to be surrounded by an element isolation region, the field-effect transistors each extending in a first direction along the main surface of the semiconductor substrate, and being arranged side by side in the first direction;   one or more impurity diffusion layers formed over an upper surface of the support substrate below the field-effect transistors, the impurity diffusion layer having a lower resistance than that of the support substrate; and   a plurality of metal wirings formed above the field-effect transistors for supplying a predetermined potential to the impurity diffusion layers,   wherein the one or more impurity diffusion layers and the metal wirings are electrically coupled to each other via a plurality of first connection portions formed through the insulating layer and the element isolation region between the field-effect transistors adjacent to each other in the first direction.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the one or more impurity diffusion layers are of the same conduction type as the field-effect transistors formed above the one or more impurity diffusion layers. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein each of the field-effect transistors has a gate electrode, and
 wherein the gate electrode is electrically coupled to the one or more impurity diffusion layers.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein each of the field-effect transistors includes a gate electrode, and a source/drain region formed from an upper surface to a lower surface of the semiconductor layer along the gate electrode, and
 wherein the field-effect transistor is of a fully-depleted type.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first connection portions extend in a second direction perpendicular to the first direction along the main surface of the semiconductor substrate, and
 wherein the first connection portions and the field-effect transistors are arranged side by side in the second direction.   
     
     
         6 . The semiconductor device according to  claim 1 , further comprising a plurality of second connection portions arranged in a second direction perpendicular to the first direction along the main surface of the semiconductor substrate, the second connection portion being adapted to electrically couple the one or more impurity diffusion layers to the metal wirings through the element isolation region and the insulating layer, and
 wherein the field-effect transistors are arranged between the adjacent second connection portions.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein each of the field-effect transistors includes the gate electrode extending in the first direction, and
 wherein the second connection portions extend in the first direction and are arranged side by side in the first direction.   
     
     
         8 . A semiconductor device, comprising:
 a semiconductor substrate with an SOI structure including a support substrate, an insulating layer formed over the support substrate, and a semiconductor layer formed over the insulating layer;   a plurality of field-effect transistors formed over a main surface of the semiconductor substrate;   a gate electrode formed over the main surface of the semiconductor substrate via a gate insulating film;   source/drain regions formed in the semiconductor layer at the main surface of the semiconductor substrate so as to sandwich therebetween the semiconductor layer under the gate electrode;   an element isolation region formed over the main surface of the semiconductor substrate;   a plurality of impurity diffusion layers formed over an upper surface of the support substrate below the field-effect transistors;   a plurality of metal wirings formed above the gate electrode for supplying a predetermined potential to the impurity diffusion layers; and   a connection portion for electrically coupling each of the impurity diffusion layers to each of the metal wirings through the element isolation region and the insulating layer,   wherein each of the impurity diffusion layers has the same conduction type as the source/drain region located above the diffusion layer.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the gate electrode is electrically coupled to the impurity diffusion layers. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein the source/drain region is formed from an upper surface to a lower surface of the semiconductor layer, and
 wherein the field-effect transistors are of a fully depleted type.   
     
     
         11 . The semiconductor device according to  claim 8 , wherein the field-effect transistors include an n-channel field-effect transistor and a p-channel field-effect transistor. 
     
     
         12 . A manufacturing method of a semiconductor device including a field-effect transistor formed over a semiconductor substrate with an SOI structure, comprising the steps of:
 (a) preparing the semiconductor substrate including a support substrate, an insulating layer formed over the support substrate, and a semiconductor layer formed over the insulating layer;   (b) after the step (a), forming an element isolation region at a main surface of the semiconductor substrate;   (c) after the step (b), forming a first impurity diffusion layer of a first conduction type over an upper surface of the support substrate by implanting impurities of the first conduction type from the main surface of the semiconductor substrate into the main surface of the semiconductor substrate, the first impurity diffusion layer having a lower resistance than that of the support substrate;   (d) after the step (b), forming a second impurity diffusion layer of a second conduction type in the semiconductor layer by implanting impurities of a second conduction type from the main surface of the semiconductor substrate into the main surface of the semiconductor substrate,   (e) after the steps (c) and (d), forming the field-effect transistors including a gate electrode and source/drain regions of the first conduction type over an upper surface of the semiconductor layer;   (f) after the step (e), forming a silicide layer over a surface of each of the gate electrode and the source/drain regions;   (g) after the step (f), forming a first insulating film over the main surface of the semiconductor substrate so as to cover the main surface of the semiconductor substrate including the element isolation region, the gate electrode, the source/drain region, and the silicide layer,   (h) after the step (g), forming a second insulating film over the first insulating film,   (i) after the step (h), respectively forming a first contact hole for exposing an upper surface of the silicide layer located over each of the source/drain regions and the gate electrode, and a second contact hole for exposing an upper surface of the first impurity diffusion layer directly under the element isolation region by etching; and   (j) after the step (i), respectively forming connection portions in the first and second contact holes,   wherein in the step (i), the first and second contact holes are formed in the same etching step.   
     
     
         13 . The manufacturing method of a semiconductor device according to  claim 12 , wherein after the step (g) and before the step (h), a part of the first insulating film formed over the element isolation region is removed and opened,
 wherein in the step (i), an upper surface of the element isolation region in an area where the second contact hole is to be formed is exposed,   wherein in the step (i), the second contact hole is formed to pass through an area where the first insulating film is to be removed, and   wherein in the etching step of forming the second contact hole, the first insulating film is not removed.   
     
     
         14 . The manufacturing method of a semiconductor device according to  claim 13 , wherein an opening formed by removing the part of the first insulating film after the step (g) and before the step (h) has a diameter in a direction along the main surface of the semiconductor substrate larger than that in the same direction of the second contact hole formed in the step (i). 
     
     
         15 . The manufacturing method of a semiconductor device according to  claim 12 , wherein in the step (i), the first insulating film and the silicide layer are used as an etching stopper film. 
     
     
         16 . The manufacturing method of a semiconductor device according to  claim 12 , wherein in the step (e), the silicide layer containing CoSi 2  is formed over the upper surface of each of the gate electrode and the source/drain regions, and
 wherein in the step (g), the first insulating film containing SiN is formed over the main surface of the semiconductor substrate.   
     
     
         17 . A manufacturing method of a semiconductor device including a field-effect transistor formed over a semiconductor substrate with an SOI structure, comprising the steps of:
 (a) preparing the semiconductor substrate including a support substrate, an insulating layer formed over the support substrate, and a semiconductor layer formed over the insulating layer;   (b) after the step (a), forming an element isolation region at a main surface of the semiconductor substrate;   (c) after the step (b), forming a first impurity diffusion layer of a first conduction type over an upper surface of the support substrate by implanting impurities of the first conduction type from the main surface of the semiconductor substrate into the main surface of the semiconductor substrate, the first impurity diffusion layer having a lower resistance than that of the support substrate;   (d) after the step (b), forming a second impurity diffusion layer of a second conduction type in the semiconductor layer by implanting impurities of the second conduction type from the main surface of the semiconductor substrate into the main surface of the semiconductor substrate,   (e) after the steps (c) and (d), forming the field-effect transistors including a gate electrode and source/drain regions of the first conduction type over an upper surface of the semiconductor layer;   (f) after the step (e), forming a first insulating film over a main surface of the semiconductor substrate so as to cover the main surface of the semiconductor substrate including the element isolation region, the gate electrode, and the source/drain region;   (g) after the step (f), forming a second insulating film over the first insulating film;   (h) after the step (g), forming a first contact hole reaching an upper surface of each of the gate electrode and the source/drain region from an upper surface of the second insulating film by etching to expose the upper surface of each of the gate electrode and the source/drain region;   (i) after the step (g), forming a second contact hole reaching an upper surface of the support substrate directly under the element isolation region from the upper surface of the second insulating film by etching to expose an upper surface of the first impurity diffusion layer directly under the element isolation region; and   (j) after the steps (h) and (i), respectively forming connection portions in the first and second contact holes,   wherein the first and second contact holes are formed in different steps.   
     
     
         18 . The manufacturing method of a semiconductor device according to  claim 17 , wherein after the step (g) and before the step (h), a part of the first insulating film formed over the element isolation region is removed and opened,
 wherein in the step (i), an upper surface of the element isolation region in an area where the second contact hole is to be formed is exposed, and   wherein in the step (i), the second contact hole is formed to pass through an area where the first insulating film is to be removed, and   wherein in the etching step of forming the second contact hole, the first insulating film is not removed.   
     
     
         19 . The manufacturing method of a semiconductor device according to  claim 18 , wherein an opening formed by removing the part of the first insulating film after the step (g) and before the step (h) has a diameter in a direction along the main surface of the semiconductor substrate larger than that in the same direction of the second contact hole formed in the step (i). 
     
     
         20 . The manufacturing method of a semiconductor device according to  claim 17 , wherein in the step (e), a silicide layer containing CoSi 2  is formed over an upper surface of each of the gate electrode and the source/drain region, and
 wherein in the step (g), the first insulating film containing SiN is formed over the main surface of the semiconductor substrate.