Carrier-free semiconductor package and fabrication method

Abstract

A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

1 . A method for fabricating a carrier-free semiconductor package, comprising the steps of:
 preparing a metal carrier having a first surface with a plurality of recess grooves and a plurality of metal studs complementary to the recess grooves and a second surface opposite to the first surface;   filling the recess grooves with a first encapsulant, in a manner that upper surfaces of the metal studs are exposed from the first encapsulant;   disposing a semiconductor chip on the first encapsulant and electrically connecting the semiconductor chip to the metal studs;   forming a second encapsulant on the first surface of the metal carrier to encapsulate the semiconductor chip; and   removing a portion of the metal carrier from the second surface thereof so as to expose lower surfaces of the metal studs and the first encapsulant.   
     
     
         2 . The method of  claim 1 , further comprising implanting solder balls on the lower surfaces of the metal studs, respectively, and performing a singulation process. 
     
     
         3 . The method of  claim 1 , wherein the upper surfaces of the metal studs are covered with a plating layer such that the semiconductor chip is electrically connected to the plating layer through wire bonding or in a flip-chip manner. 
     
     
         4 . The method of  claim 3 , wherein the plating layer is formed on the upper surfaces of the metal studs by spotting plating silver or dipping an organic solderable protection (OSP) film. 
     
     
         5 . The method of  claim 3 , before forming the plating layer, further comprising forming on the upper surfaces of the metal studs a metal layer having a thickness of 3 to 20 μm, such that the metal layer is covered by the plating layer after the plating layer is formed over the metal layer. 
     
     
         6 . The method of  claim 1 , wherein the metal carrier with the recess grooves and the metal studs is fabricated by the following steps of:
 providing a metal carrier having a first surface and an opposite second surface, forming a patterned first resist layer on the first surface of the metal carrier, and forming a second resist layer to cover the second surface of the metal carrier; and   removing a portion of the metal carrier free from being covered by the first resist layer by half-etching so as to form the recess grooves and the metal studs complementary to the plurality of recess grooves on the first surface of the metal carrier.   
     
     
         7 . The method of  claim 3 , wherein the metal carrier with the recess grooves and the metal studs is fabricated by the following steps of:
 providing a metal carrier having a first surface and an opposite second surface, forming a patterned first resist layer on the first surface of the metal carrier, and forming a second resist layer to cover the second surface of the metal carrier, wherein the patterned first resist layer has a plurality of openings for exposing the metal carrier;   forming a plating layer in the openings of the patterned first resist layer;   removing the patterned first resist layer and the second resist layer; and   performing a half-etching process on the first surface of the metal carrier by using the plating layer as an etching resist layer to remove a portion of the metal carrier, thereby forming the plurality of recess grooves and the plurality of metal studs complementary to the recess grooves on the first surface of the metal carrier.   
     
     
         8 . The method of  claim 1 , wherein each of the metal studs is a solder pad or a die pad. 
     
     
         9 . The method of  claim 1 , wherein the first encapsulant is made of one or more materials selected form the group consisting of a molding compound, a solder mask and an epoxy resin. 
     
     
         10 . A method for fabricating a carrier-free semiconductor package, comprising the steps of:
 preparing a metal carrier having a first surface with a plurality of recess grooves and a plurality of metal studs complementary to the recess grooves and a second surface opposite to the first surface;   filling the recess grooves with a first encapsulant in a manner that upper surfaces of the metal studs are exposed from the first encapsulant, wherein the first encapsulant that a top surface and an opposing bottom surface;   forming a plurality of conductive traces on the top surface of the first encapsulant and the upper surfaces of the metal studs and electrically connected to the metal studs;   disposing a semiconductor chip on the first encapsulant and electrically connecting the semiconductor chip to each of the conductive traces;   forming a second encapsulant on the first surface of the metal carrier to encapsulate the semiconductor chip and each of the conductive traces; and   removing a portion of the metal carrier from the second surface thereof so as to expose lower surfaces of the metal studs and the bottom surface of the first encapsulant.   
     
     
         11 - 13 . (canceled) 
     
     
         14 . The method of  claim 10 , wherein the conductive traces are formed by the following steps of:
 forming a conductive layer on the top surface of the first encapsulant and the upper surfaces of the metal studs;   forming a patterned third resist layer on the conductive layer and forming a plurality of openings in the patterned third resist layer; and   forming the plurality of conductive traces in the openings of the third resist layer and electrically connected to the metal studs.   
     
     
         15 . The method of  claim 14 , wherein the formation of the conductive traces further comprises forming a patterned buffer layer on the top surface of the first encapsulant and the upper surfaces of the metal studs so as to expose each of the metal studs from the buffer layer before formation of the conductive traces. 
     
     
         16 . The method of  claim 15 , wherein the patterned buffer layer is made of benzo-cyclo-butene (BCB) or polyimide (PI). 
     
     
         17 . The method of  claim 14 , further comprising removing the third resist layer and the conductive layer covered by the third resist layer. 
     
     
         18 . The method of  claim 14 , wherein each of the openings of the patterned third resist layer defines positions of each of the conductive traces and each of the metal studs serving as a die pad. 
     
     
         19 - 21 . (canceled) 
     
     
         22 . A method for fabricating a carrier-free semiconductor package, comprising the steps of:
 preparing a metal carrier having a first surface with a plurality of recess grooves and metal studs and a second surface opposite to the first surface;   filling the recess grooves with a first encapsulant, with upper surfaces of the metal studs being exposed from the first encapsulant, wherein the first encapsulant has a top surface and an opposing bottom surface;   forming a plurality of conductive traces on the top surface of the first encapsulant and the upper surfaces of the metal studs and electrically connected to the metal studs;   forming a second encapsulant on the first encapsulant and each of the conductive traces, each of the conductive traces being partially exposed from the second encapsulant;   forming build-up traces on the second encapsulant and the exposed parts of the conductive traces;   forming a plating layer on each of terminals of the build-up traces;   disposing a semiconductor chip on the second encapsulant and electrically connecting the semiconductor chip to the build-up traces;   forming a third encapsulant on the second encapsulant to encapsulate the semiconductor chip and each of the build-up traces; and   removing a part of the metal carrier from the second surface thereof so as to expose lower surfaces of the metal studs and the bottom surface of the first encapsulant.   
     
     
         23 . The method of  claim 22 , wherein the step of forming the conductive traces further comprises forming a plurality of die pads on the first encapsulant and the metal studs, and the die pads are at least partially exposed from the second encapsulant. 
     
     
         24 - 25 . (canceled) 
     
     
         26 . A carrier-free semiconductor package, comprising:
 a plurality of metal studs spaced from each other;   a first encapsulant having a top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;   a semiconductor chip disposed on the top surface of the first encapsulant and electrically connected to each of the metal studs; and   a second encapsulant formed on the top surface of the first encapsulant and encapsulating the semiconductor chip.   
     
     
         27 . The package of  claim 26 , further comprising a plurality of solder balls implanted on the lower surfaces of the metal studs, respectively. 
     
     
         28 . The package of  claim 26 , wherein the upper surfaces of the metal studs are covered with a plating layer such that the semiconductor chip is electrically connected to the plating layer through bonding wires or in a flip-chip manner. 
     
     
         29 . The package of  claim 28 , wherein the plating layer is a silver plating layer or an OSP film. 
     
     
         30 . The package of  claim 26 , wherein each of the metal studs is a solder pad or a die pad. 
     
     
         31 . A carrier-free semiconductor package, comprising:
 a plurality of metal studs spaced from each other;   a first encapsulant having a top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;   a plurality of conductive traces disposed on the top surface of the first encapsulant and electrically connected to each of the metal studs;   a semiconductor chip disposed on the top surface of the first encapsulant and electrically connected to each of the conductive traces; and   a second encapsulant formed on the top surface of the first encapsulant and encapsulating the semiconductor chip and each of the conductive traces.   
     
     
         32 - 35 . (canceled) 
     
     
         36 . The package of  claim 31 , further comprising a patterned buffer layer formed and sandwiched among the first encapsulant, the plurality of conductive traces and the second encapsulant, such that each of the metal studs is exposed form the patterned buffer layer. 
     
     
         37 . The package of  claim 36 , wherein the patterned buffer layer is made of BCB or PI. 
     
     
         38 . A carrier-free semiconductor package, comprising:
 a plurality of metal studs spaced from each other;   a first encapsulant having an top surface and an opposite bottom surface, wherein sides of the metal studs are encapsulated by the first encapsulant, and upper and lower surfaces of the metal studs are exposed from the top and bottom surfaces of the first encapsulant, respectively;   a plurality of conductive traces disposed on the top surface of the first encapsulant and electrically connected to the metal studs;   a second encapsulant formed on the first encapsulant and the plurality of conductive traces, each of the conductive traces being at least partially exposed from the second encapsulant;   a plurality of build-up traces disposed on the second encapsulant and the exposed conductive traces;   a semiconductor chip disposed on a top surface of the second encapsulant and electrically connected to the build-up traces; and   a third encapsulant formed on the top surface of the second encapsulant and encapsulating the semiconductor chip and each of the build-up traces.   
     
     
         39 . The package of  claim 38 , further comprising a plurality of die pads disposed on the top surface of the first encapsulant and electrically connected to each of the metal studs, upper surfaces of the die pads being partially covered by the second encapsulant. 
     
     
         40 - 43 . (canceled)