Non-volatile semiconductor memory device and depletion-type mos transistor

Abstract

A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via agate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.

1 . A method of manufacturing a non-volatile semiconductor memory device, the non-volatile semiconductor memory device comprising:
 a memory cell array including memory cell transistors arranged therein, the memory cell transistors being provided with a charge accumulation layer formed on a semiconductor substrate via a gate insulating film; and   a peripheral circuit configured to drive the memory cell transistors, the peripheral circuit including a first transistor,   the method comprising:   forming a first element isolation insulating film on the semiconductor substrate to form a first active area of the first transistor;   implanting a first conductivity type impurity into a first region of the semiconductor substrate to form a first channel region of the first transistor in a part of the first active area;   stacking a first gate insulating layer of the first transistor and a first gate electrode of the first transistor on a part of the first channel region; and   implanting the first conductivity type impurity into a second region of the semiconductor substrate by using the first gate electrode as a mask to form overlapping regions where the second region overlaps the first channel region and to form first source-drain regions of the first transistor where the second region excluding the overlapping regions in the first active area.   
     
     
         2 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , wherein,
 the first transistor has a gate width parallel to a first direction, and   a length of the first region in the first direction is longer than a length of the first active area in the first direction.   
     
     
         3 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 2 , wherein
 the length of the first region in the first direction is shorter than a length of the first gate electrode in the first direction.   
     
     
         4 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , wherein
 the first channel region is formed shallower than the first source-drain regions from the surface of the first active area.   
     
     
         5 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , wherein,
 a concentration of the first conductivity type impurity in the first source-drain regions is larger than a concentration of the first conductivity type impurity in the first channel region, and   a concentration of the first conductivity type impurity in the overlapping regions is larger than a concentration of the first conductivity type impurity in the first source-drain regions.   
     
     
         6 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , further comprising:
 implanting the first conductivity type impurity into a part of the first source-drain regions to form contact regions of the first transistor, wherein   a concentration of the first conductivity type impurity in the contact regions is larger than a concentration of the first conductivity type impurity in the first source-drain regions.   
     
     
         7 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 6 , wherein
 the contact regions are formed in a position inside from the edge of the first source-drain regions.   
     
     
         8 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , wherein
 an impurity implanted in the first region and an impurity implanted in the second region are of different elements.   
     
     
         9 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 8 , wherein
 an impurity implanted in the first region is arsenic (As) and an impurity implanted in the second region is phosphorus (P).   
     
     
         10 . The method of manufacturing a non-volatile semiconductor memory device according to  claim 1 , further comprising:
 forming a second element isolation insulating film on the semiconductor substrate to form a second active area of a second transistor, simultaneously with forming the first element isolation insulating film;   implanting a first conductivity type impurity into a third region of the semiconductor substrate to form a second channel region of the second transistor in entire the second active area, simultaneously with forming the first channel region;   stacking a second gate insulating layer and a second gate electrode on a part of the second channel region; and   implanting the first conductivity type impurity into the second channel region by using the second gate electrode as a mask to form second source-drain regions simultaneously with forming the first source-drain regions.   
     
     
         11 . A method of manufacturing a depletion-type MOS transistor, comprising:
 forming a first element isolation insulating film on a semiconductor substrate to form a first active area;   implanting a first conductivity type impurity into a first region of the semiconductor substrate to form a first channel region in a part of the first active area;   stacking a first gate insulating layer and a first gate electrode on a part of the first channel region; and   implanting the first conductivity type impurity into a second region of the semiconductor substrate by using the first gate electrode as a mask to form overlapping regions where the second region overlaps the first channel region and to form first source-drain regions where the second region excluding the overlapping regions in the first active area.   
     
     
         12 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , wherein,
 the depletion-type MOS transistor has a gate width parallel to a first direction, and   a length of the first region in the first direction is longer than a length of the first active area in the first direction.   
     
     
         13 . The method of manufacturing a depletion-type MOS transistor according to  claim 12 , wherein
 the length of the first region in the first direction is shorter than a length of the first gate electrode in the first direction.   
     
     
         14 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , wherein
 the first channel region is formed shallower than the first source-drain regions from the surface of the first active area.   
     
     
         15 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , wherein,
 a concentration of the first conductivity type impurity in the first source-drain regions is larger than a concentration of the first conductivity type impurity in the first channel region, and   a concentration of the first conductivity type impurity in the overlapping regions is larger than a concentration of the first conductivity type impurity in the first source-drain regions.   
     
     
         16 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , further comprising:
 implanting the first conductivity type impurity into a part of the first source-drain regions to form contact regions, wherein   a concentration of the first conductivity type impurity in the contact regions is larger than a concentration of the first conductivity type impurity in the first source-drain regions.   
     
     
         17 . The method of manufacturing a depletion-type MOS transistor according to  claim 16 , wherein
 the contact regions are formed in a position inside from the edge of the first source-drain regions.   
     
     
         18 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , wherein
 an impurity implanted in the first region and an impurity implanted in the second region are of different elements.   
     
     
         19 . The method of manufacturing a depletion-type MOS transistor according to  claim 18 , wherein
 an impurity implanted in the first region is arsenic (As) and an impurity implanted in the second region is phosphorus (P).   
     
     
         20 . The method of manufacturing a depletion-type MOS transistor according to  claim 11 , further comprising:
 forming a second element isolation insulating film on the semiconductor substrate to form a second active area, simultaneously with forming the first element isolation insulating film;   implanting a first conductivity type impurity into a third region of the semiconductor substrate to form a second channel region in entire the second active area, simultaneously with forming the first channel region;   stacking a second gate insulating layer and a second gate electrode on a part of the second channel region; and   implanting the first conductivity type impurity into the second channel region by using the second gate electrode as a mask to form second source-drain regions simultaneously with forming the first source-drain regions.