Interconnect structure and method of manufacturing a damascene structure

Abstract

An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

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         10 . A method of manufacturing a damascene structure on a semiconductor substrate, comprising:
 forming at least one opening in a dielectric material;   coating sidewalls defining the opening with a tantalum- and nitrogen-containing first barrier layer;   treating the first barrier layer to form a tantalum-rich zone and a tantalum nitride zone, wherein the nitrogen content of the tantalum nitride zone is greater than the nitrogen content of the tantalum-rich zone, the tantalum nitride zone being interposed between the dielectric material and the tantalum-rich zone;   coating the first barrier layer with a ruthenium-containing second barrier layer;   treating the second barrier layer to form a ruthenium oxide zone and a ruthenium zone, the ruthenium zone interposed between the tantalum-rich zone and the ruthenium oxide zone; and   treating the ruthenium oxide zone to form a ruthenium-rich zone, the ruthenium oxide zone interposed between the ruthenium zone and ruthenium-rich zone.   
     
     
         11 . The method of  claim 10 , further comprising coating a copper seed layer over the second barrier layer, filling the opening with copper, and planarizing a top surface of the dielectric. 
     
     
         12 . The method of  claim 10 , wherein the sidewalls of the first barrier layer are coated by atomic layer deposition (ALD), thermal ALD, plasma enhanced ALD, or hot filament ALD. 
     
     
         13 . The method of  claim 12 , wherein the ALD is performed with a tantalum precursor selected from the group consisting of pentakis (ethylmethylamino) tantalum (PEMAT), pentakis (diethylamino) tantalum (PDEAT), pentakis (dimethylamino) tantalum (PDMAT), t-butylimino tris(diethylamino) tantalum (TBTDET), t-butylimino tri-(ethylmethylamino) tantalum (TBTEMT) and tantalum halides. 
     
     
         14 . The method of  claim 10 , wherein the treating of the first barrier layer is performed by hydrogen reduction or by thermal hydrogen reduction or by exposure to a hydrogen-containing plasma. 
     
     
         15 . The method of  claim 14 , wherein the hydrogen-containing plasma is generated in an inductively coupled plasma apparatus, a capacitively coupled plasma apparatus, or a downstream plasma processing apparatus. 
     
     
         16 . The method of  claim 10 , wherein the second barrier layer is formed by atomic layer deposition (ALD), thermal ALD, plasma enhanced ALD, or hot filament ALD. 
     
     
         17 . The method of  claim 16 , wherein the ALD is performed with a bis(cyclopentadienyl) ruthenium (RuCp 2 ) or a bis(ethylcyclopentadienyl) ruthenium (Ru(CpEt) 2 ) precursor. 
     
     
         18 . The method of  claim 10 , wherein the treating of the second barrier layer to form the ruthenium oxide zone is performed by exposure to an oxygen-containing plasma. 
     
     
         19 . The method of  claim 10 , wherein the treating of the ruthenium oxide zone to form the ruthenium-rich zone is performed by hydrogen reduction or by thermal hydrogen reduction or by exposure to a hydrogen-containing plasma. 
     
     
         20 . The method of  claim 10 , wherein all coating and treating are performed in situ in separate chambers, while maintaining the semiconductor substrate in a vacuum environment.