Semiconductor Device With Resistor Pattern And Method Of Fabricating The Same

Abstract

Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.

1 . A semiconductor device comprising:
 a device isolation layer disposed in a substrate to define an active region;   source and drain regions formed in the active region;   a gate electrode formed on the active region between the source and drain and including an overlapping region on the isolation region;   a gate insulation layer interposed between the gate electrode and the active region;   a resistor pattern formed on the device isolation layer;   resistor spacers disposed on sidewalls of the resistor pattern;   a first interlayer dielectric layer disposed over the resistor pattern, the gate electrode and the substrate;   a planarized second interlayer dielectric layer disposed on the first interlayer dielectric layer; and   a resistor electrode connected to an end portion of the resistor pattern,   wherein the gate electrode includes a polysilicon layer and a silicide layer that are sequentially stacked on the gate insulation layer,   wherein the resistor pattern comprises a polysilicon layer and a silicide layer stacked on the end portion except of a majority of the polysilicon layer, and   wherein the resistor electrode is connected to the silicide layer.   
     
     
         2 . The device of  claim 1 , further comprising contact plugs connected to the source and the drain regions through the second and first interlayer dielectric layer. 
     
     
         3 . The device of  claim 1 , wherein the resistor pattern is in direct contact with the device isolation layer. 
     
     
         4 . The device of  claim 1 , wherein the device isolation layer includes a first sidewall portion having a negative slope in the substrate and second sidewall portion having a positive slope over the substrate,
 wherein a length of the first sidewall portion is longer than that of the second sidewall portion.   
     
     
         5 . The device of  claim 2 , wherein the first interlayer dielectric layer contacts the resistor spacers. 
     
     
         6 . The device of  claim 2 , wherein the gate insulation layer is multi-layered and includes at least one charge storage dielectric layer. 
     
     
         7 . The device of  claim 6 , wherein the charge storage dielectric layer comprises silicon nitride. 
     
     
         8 . The device of  claim 6 , wherein the gate electrode further comprises an overlapping region on the isolation region. 
     
     
         9 . The device of  claim 6 , wherein the resistor pattern is in direct contact with the device isolation layer. 
     
     
         10 . The device of  claim 6 , wherein the first interlayer dielectric layer contacts the resistor spacers. 
     
     
         11 . A semiconductor device comprising:
 a device isolation layer disposed in a substrate to define an active region;   source and drain regions formed in the active region;   a gate electrode formed on the active region between the source and drain regions and a first polysilicon layer and a first metal silicide layer;   a gate insulation layer interposed between the gate electrode and the active region;   a resistor pattern formed on the device isolation layer and including a first portion formed of a second polysilicon layer (pattern) and a second portion formed of a second polysilicon layer (pattern) and a second metal silicide layer (pattern);   resistor spacers disposed on sidewalls of the resistor pattern;   a first dielectric layer disposed over the gate electrode and the active region, and including at least one of contact plugs connected to at least one of the source and the drain regions;   a resistor electrode connected to an end portion of the resistor pattern; and   a second dielectric layer disposed on the first portion of the resistor pattern,   wherein the second dielectric layer formed at different step of the first dielectric layer, and   wherein the resistor electrode contacts the silicide pattern.   
     
     
         12 . The device of  claim 11 , wherein the device isolation layer includes a first sidewall portion having a negative slope in the substrate and second sidewall portion having a positive slope over the substrate, wherein a length of the first sidewall portion is longer than that of the second sidewall portion. 
     
     
         13 . The device of  claim 11 , wherein the gate insulation layer is multi-layered and includes at least one charge storage dielectric layer. 
     
     
         14 . The device of  claim 13 , wherein the charge storage dielectric layer comprises silicon nitride.