Novel method to enhance channel stress in cmos processes
Abstract
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
Claims
exact text as granted — not AI-modified1 . A method of fabricating an integrated circuit, comprising:
providing a partially processed silicon substrate with isolation structures and a
gate dielectric formed thereon;
depositing an amorphous gate;
forming a gate over a channel region;
applying stress to said channel region; and
with said gate in an amorphous state, performing a source and drain anneal
wherein said source and drain anneal converts the amorphous gate to polycrystalline.
2 . The method of claim 1 in which a transistor is PMOS and said stress is applied to said channel region by forming a compressive stress layer over said amorphous gate prior to said source and drain anneal.
3 . The method of claim 1 in which a transistor is NMOS and said stress is applied to said channel region by forming a tensile stress layer over said amorphous gate prior to said source and drain anneal.
4 . The method of claim 3 in which said gate material is amorphous silicon.
5 . The method of claim 4 in which the maximum processing temperature between said amorphous silicon deposition and said source and drain anneal is 560 C. degrees.Join the waitlist — get patent alerts
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