Microelectronic package and method of manufacturing same

Abstract

A microelectronic package includes a substrate ( 110 ), a die ( 120 ) embedded within the substrate, the die having a front side ( 121 ) and a back side ( 122 ) and a through-silicon-via ( 123 ) therein, build-up layers ( 130 ) built up over the front side of the die, and a power plane ( 140 ) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate ( 210 ), a first die ( 220 ) and a second die ( 260 ) embedded in the substrate and having a front side ( 221, 261 ) and a back side ( 222, 262 ) and a through-silicon-via ( 223, 263 ) therein, build-up layers ( 230 ) over the front sides of the first and second dies, and an electrically conductive structure ( 240 ) in physical contact with the back sides of the first and second dies.

1 . A microelectronic package comprising:
 a substrate;   a die embedded within the substrate, the die having a front side and an opposing back side and further having at least one through-silicon-via therein;   a plurality of build-up layers adjacent to and built up over the front side of the die; and   a power plane adjacent to and in physical contact with the back side of the die.   
     
     
         2 . The microelectronic package of  claim 1  wherein:
 the power plane comprises copper. 
 
     
     
         3 . The microelectronic package of  claim 1  further comprising:
 a passive component attached to the power plane. 
 
     
     
         4 . The microelectronic package of  claim 1  further comprising:
 a protective layer over the power plane. 
 
     
     
         5 . The microelectronic package of  claim 1  wherein:
 the power plane has a recess therein; and 
 the die is at least partially located within the recess. 
 
     
     
         6 . The microelectronic package of  claim 1  wherein:
 the die has a die perimeter; 
 an extension of the die perimeter through the build-up layers defines a die area; and 
 the build-up layers contain a first plurality of vias outside the die area and a second plurality of vias inside the die area. 
 
     
     
         7 . The microelectronic package of  claim 6  wherein:
 the first plurality of vias electrically connect the power plane and the substrate to each other; and 
 the second plurality of vias electrically connect the die and the substrate to each other. 
 
     
     
         8 . A microelectronic package comprising:
 a substrate;   a first die and a second die, both of which are embedded in the substrate, both of which have a front side and an opposing back side, and both of which have at least one through-silicon-via therein;   a plurality of build-up layers adjacent to and built up over the front sides of the first and second dies; and   an electrically conductive structure adjacent to and in physical contact with the back sides of the first and second dies.   
     
     
         9 . The microelectronic package of  claim 8  wherein:
 the electrically conductive structure comprises:
 an interconnect that electrically connects the back sides of the first and second dies to each other; and 
 a die connection pad. 
 
 
     
     
         10 . The microelectronic package of  claim 9  wherein:
 the first die has a first die perimeter and the second die has a second die perimeter; 
 an extension of the first and second die perimeters through the build-up layers defines a die area; and 
 the build-up layers contain a first plurality of vias outside the die area and a second plurality of vias inside the die area. 
 
     
     
         11 . The microelectronic package of  claim 10  wherein:
 the first plurality of vias electrically connect the die connection pad and the substrate to each other; and 
 the second plurality of vias electrically connect the first and second dies and the substrate to each other. 
 
     
     
         12 . The microelectronic package of  claim 8  wherein:
 the electrically conductive structure comprises copper. 
 
     
     
         13 . The microelectronic package of  claim 8  further comprising:
 a protective layer over the electrically conductive structure. 
 
     
     
         14 . The microelectronic package of  claim 8  wherein:
 the electrically conductive structure has a recess therein; and 
 the first die and the second die are at least partially located within the recess. 
 
     
     
         15 . A method of manufacturing a microelectronic package, the method comprising:
 providing an electrically conductive carrier;   providing a die having a front side, an opposing back side, and at least one through-silicon-via therein;   attaching the back side of the die to the electrically conductive carrier;   forming a plurality of build-up layers over the front side of the die, the build-up layers and the electrically conductive carrier forming part of a substrate of the microelectronic package; and   patterning the electrically conductive carrier in order to form an electrically conductive component of the microelectronic package.   
     
     
         16 . The method of  claim 15  wherein:
 the electrically conductive component is a power plane. 
 
     
     
         17 . The method of  claim 16  further comprising:
 electrically connecting the power plane to a power source; and 
 electrically connecting the substrate to the power source. 
 
     
     
         18 . The method of  claim 15  wherein:
 the microelectronic package further comprises a second die; and 
 the electrically conductive component is an electrical connection between the die and the second die. 
 
     
     
         19 . The method of  claim 15  wherein:
 the electrically conductive carrier comprises copper. 
 
     
     
         20 . The method of  claim 15  further comprising:
 forming a plurality of connection pads adjacent to the electrically conductive component. 
 
     
     
         21 . The method of  claim 15  wherein:
 providing the electrically conductive carrier comprises providing a copper foil attached to a sacrificial core; 
 the method further comprises separating the copper foil from the sacrificial core after the build-up layers are completed; and 
 patterning the electrically conductive carrier in order to form the electrically conductive component of the microelectronic package comprises patterning the copper foil.