Microelectronic package and method of manufacturing same

Abstract

A microelectronic package includes a first substrate ( 120 ) having a first surface area ( 125 ) and a second substrate ( 130 ) having a second surface area ( 135 ). The first substrate includes a first set of interconnects ( 126 ) having a first pitch ( 127 ) at a first surface ( 121 ) and a second set of interconnects ( 128 ) having a second pitch ( 129 ) at a second surface ( 222 ). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects ( 236 ) having a third pitch ( 237 ) and internal electrically conductive layers ( 233, 234 ) connected to each other with a microvia ( 240 ). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

1 . A method of manufacturing a microelectronic package, the method comprising:
 providing a first substrate;   attaching the first substrate to a second substrate in order to form a substrate assembly, the second substrate having first and second internal electrically conductive layers that are connected to each other with a microvia;   performing a test on the substrate assembly in order to obtain a test result;   if, and only if, the test result satisfies a pre-determined condition, attaching a die to the substrate assembly.   
     
     
         2 . The method of  claim 1  further comprising:
 reinforcing the substrate assembly. 
 
     
     
         3 . The method of  claim 1  wherein:
 the first substrate has a first surface area; 
 the first substrate comprises a first set of interconnects having a first pitch at a first surface thereof and a second set of interconnects having a second pitch at a second surface thereof; and 
 the first pitch is smaller than the second pitch. 
 
     
     
         4 . The method of  claim 3  wherein:
 the second substrate has a second surface area; 
 the second substrate is coupled to the first substrate using the second set of interconnects; 
 the second substrate comprises a third set of interconnects having a third pitch; 
 the second pitch is smaller than the third pitch; and 
 the first surface area is smaller than the second surface area. 
 
     
     
         5 . A method of manufacturing a microelectronic package, the method comprising:
 providing a die;   attaching the die to a first substrate in order to form a die assembly;   performing a test on the die assembly in order to obtain a test result;   if, and only if, the test result satisfies a pre-determined condition, attaching the die assembly to a second substrate, the second substrate having first and second internal electrically conductive layers that are connected to each other with a microvia.   
     
     
         6 . The method of  claim 5  further comprising:
 reinforcing the die assembly. 
 
     
     
         7 . The method of  claim 5  wherein:
 the first substrate has a first surface area; 
 the first substrate comprises a first set of interconnects having a first pitch at a first surface thereof and a second set of interconnects having a second pitch at a second surface thereof; and 
 the first pitch is smatter than the second pitch. 
 
     
     
         8 . The method of  claim 7  wherein:
 the second substrate has a second surface area; 
 the second substrate is coupled to the first substrate using the second set of interconnects; 
 the second substrate comprises a third set of interconnects having a third pitch; 
 the second pitch is smaller than the third pitch; and 
 the first surface area is smaller than the second surface area.