Electrical-overstress protection circuit for an integrated circuit

Abstract

An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

1 . An electrical-overstress (EOS) protection circuit for an electronic device, comprising:
 series-connected resistors electrically coupled between an input and an output;   a mode-control switch electrically coupled between the output and a ground; and   a bias circuit electrically coupled to the input with a configuration for generation of a mode-control signal to control the mode-control switch;   wherein the mode-control signal is present with the mode-control switch being open in a normal mode and closed in an EOS mode.   
     
     
         2 . The EOS protection circuit of  claim 1 , wherein the series-connected resistors are arranged and numbered in a way such that voltage drop across each said resistor in the EOS mode is below a specified operating voltage. 
     
     
         3 . The EOS protection circuit of  claim 1 , wherein each of the series-connected resistors is a resistor-configured metal-oxide-semiconductor (MOS) transistor. 
     
     
         4 . The EOS protection circuit of  claim 1 , wherein the bias circuit comprises a voltage divider configured to partition the input voltage among a plurality of components, and wherein the mode-control signal is derived from a node among the components. 
     
     
         5 . The EOS protection circuit of  claim 4 , wherein each component is a resistor component. 
     
     
         6 . The EOS protection circuit of  claim 5 , wherein each resistor component is a resistor-configured. MOS transistor. 
     
     
         7 . The EOS protection circuit of  claim 1 , further comprising a second mode-control switch with one end coupled to the bias circuit and another end providing the mode-control signal and being connected with a current source, and wherein the second mode-control switch is open in the normal mode and closed in the EOS mode. 
     
     
         8 . The EOS protection circuit of  claim 1 , wherein the bias circuit is arranged to generate the mode-control signal in a way such that the mode-control switch is open in the normal mode and is closed, in the EOS mode.