Lateral drain mosfet with substrate drain connection

Abstract

In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.

1 . A lateral MOSFET comprising:
 a) an active gate positioned laterally between a source region and a drain region, said drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of said monocrystalline semiconductor body;   b) a non-active gate positioned laterally above said drain region;   c) a heavy body region of a second conductivity type in contact with and below said source region; and   d) metallization extending below said upper surface of said monocrystalline body in contact with said source region and said heavy body along a lateral surface and a side surface of each of said source region and said heavy body.   
     
     
         2 . The lateral MOSFET of  claim 1  wherein a channel region of a first conductivity type lies below said active gate in an epitaxial layer of a second conductivity type opposite to said first conductivity type. 
     
     
         3 . The lateral MOSFET of  claim 1  wherein said monocrystalline semiconductor body comprises a substrate with a first epitaxial layer on said substrate, and a second epitaxial layer on said first epitaxial layer. 
     
     
         4 . The lateral MOSFET of  claim 3  wherein said substrate, said first epitaxial layer, and said second epitaxial layer are of the same conductivity type. 
     
     
         5 . The lateral MOSFET of  claim 2  wherein said channel region is part of a larger region of the same conductivity type, and said larger region has a vertical doping gradient which is not substantially uniform. 
     
     
         6 . The lateral MOSFET of  claim 2  wherein said channel region is part of a larger region of the same conductivity type, and said larger region has a vertical doping gradient which is substantially uniform. 
     
     
         7 . The lateral MOSFET of  claim 1  wherein said drain region has a substantially uniform vertical dopant concentration. 
     
     
         8 . The lateral MOSFET of  claim 1  wherein an upper portion of said drain region has a higher dopant concentration than a portion of said drain region lying below said upper portion. 
     
     
         9 . The lateral MOSFET of  claim 1  wherein an upper portion of said drain region has a lower dopant concentration than a portion of said drain region lying below said upper portion. 
     
     
         10 . A method for forming a lateral MOSFET with a substrate drain connection comprising the steps of:
 a) forming a source region and a drain region in an upper surface of a monolithic semiconductor body, and an active gate positioned above said monocrystalline semiconductor body between said source region and said drain region, said drain region extending from an upper surface of said monocrystalline semiconductor body to a bottom surface of said monocrystalline semiconductor body; and   b) forming a non-active gate positioned above said drain region.   
     
     
         11 . The method of  claim 10  wherein said monocrystalline semiconductor body comprises an epitaxial layer formed on a substrate, said epitaxial layer and said substrate being of a first conductivity type. 
     
     
         12 . The method of  claim 10  wherein said monocrystalline semiconductor body comprises a substrate with a first epitaxial layer formed on said substrate, and a second epitaxial layer formed on said first epitaxial layer, said substrate, said first epitaxial layer, and said second epitaxial layer being of a first conductivity type. 
     
     
         13 . The method of  claim 12  further including the step of forming a counter doped region of a second conductivity type opposite to said first conductivity type in an upper portion of said second epitaxial layer. 
     
     
         14 . The method of  claim 13  wherein said counter doped region is formed by gaseous diffusion. 
     
     
         15 . The method of  claim 13  wherein said counter doped region is formed by a single ion implantation. 
     
     
         16 . The method of  claim 13  wherein said counter doped region is formed by multiple ion implantations. 
     
     
         17 . The method of  claim 13  further including the step of performing a threshold voltage implant in an upper surface region of said second epitaxial layer. 
     
     
         18 . The method of  claim 13  wherein said active gate and said non-active gate are formed after said counter doped region is formed. 
     
     
         19 . The method of  claim 18  further including forming a sinker in said second epitaxial layer by performing an implant that is self aligned with the edged of the non-active gate which is farthest from said active gate. 
     
     
         20 . The method of  claim 19  wherein said sinker is formed by a single ion implantation. 
     
     
         21 . The method of  claim 19  wherein said sinker is formed by multiple ion implantations. 
     
     
         22 . The method of  claim 19  further including the steps of forming a heavy body of said second conductivity type and a source of said first conductivity type, both of which are self aligned with an edge of said active gate farthest from said sinker, said heavy body extending below said source region and having a lower dopant concentration than said source region. 
     
     
         23 . The method of  claim 22  further including forming a region of said first conductivity type that is self aligned with the edged of the non-active gate which is farthest from said active gate and is formed at the same time that said source region is formed. 
     
     
         24 . The method of  claim 22  further including forming a metal contact to said heavy body and source region, said metal contact extending below a top surface of said monocrystalline semiconductor body. 
     
     
         25 . The method of  claim 22  further including forming a metal contact to said heavy body and source region, said metal contact does not extend below a top surface of said monocrystalline semiconductor body.