Apparatuses and systems for fabricating three dimensional integrated circuits

Abstract

The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One or more embodiments of systems, apparatuses, and/or methods according to the present invention are presented.

1 . A system for processing a wafer for three-dimensional integrated circuits, the system comprising:
 a process chamber configured to process the wafer at sub-atmospheric pressure;   a wafer holder disposed in the process chamber, the wafer holder comprising a substantially rigid body configured so as to provide a substantially planar surface to contact the back side of the semiconductor wafer; the wafer holder having a fluid flow channel in fluid communication with the planar surface; and   a vacuum pump connected with the fluid flow channel configured to produce a pressure differential between the front side and back side of the semiconductor wafer.   
     
     
         2 . The system of  claim 1 , wherein the wafer holder is configured to electrostatically hold the wafer to the planar surface. 
     
     
         3 . The system of  claim 1 , wherein the wafer holder further comprises a clamp to hold the wafer to the planar surface. 
     
     
         4 . The system of  claim 1 , wherein the substantially rigid body further comprises a porous material for the planar surface to contact the back side of the wafer. 
     
     
         5 . The system of  claim 1 , wherein the substantially rigid body has a cavity and at least one structure disposed in the cavity, the at least one structure extends from the base of the cavity so as to form the planar surface. 
     
     
         6 . The system of  claim 1 , wherein the wafer has at least one hole and the substantially rigid body has a cavity and at least one structure disposed in the cavity, the at least one structure extends from the base of the cavity so as to form the planar surface, and the structure is shaped so as to minimize the impedance of gas flow through the wafer. 
     
     
         7 . The system of  claim 1 , wherein the substantially rigid body has a cavity and at least one structure disposed in the cavity, the at least one structure extends from the base of the cavity so as to form the planar surface, and the at least one structure has a knife-edge for contacting the wafer. 
     
     
         8 . The system of  claim 1 , wherein the wafer has at least one through hole configured for gas transfer from the front side of the wafer to the back side of the wafer; the vacuum pump being configured to enhance the gas transfer. 
     
     
         9 . The system of  claim 1 , wherein the wafer holder includes a surface to form a seal at the back side periphery of the wafer. 
     
     
         10 . The system of  claim 1 , wherein the wafer holder includes a pumping plate configured to support the wafer and the pumping plate has at least one hole positioned to expose an area of the wafer for an integrated circuit device. 
     
     
         11 . The system of  claim 1 , wherein the wafer holder includes a pumping plate configured to support the wafer, the pumping plate has at least one hole positioned to expose an area of the wafer for an integrated circuit device and the pumping plate is removably coupled to the wafer holder. 
     
     
         12 . The system of  claim 1 , wherein the wafer holder includes a surface to form a seal at the back side periphery of the wafer; the substantially rigid body has a cavity and at least one structure disposed in the cavity; the at least one structure extends from the base of the cavity up to the planar surface. 
     
     
         13 . The system of  claim 1 , wherein the wafer holder includes a surface to form a seal at the back side periphery of the wafer; the substantially rigid body has a cavity and at least one structure disposed in the cavity, the at least one structure extends from the base of the cavity up to the planar surface; and the structure having a knife edge for contacting the wafer. 
     
     
         14 . The system of  claim 1 , wherein the process chamber comprises a
 a chemical vapor deposition chamber,   a low-pressure chemical vapor deposition chamber,   a plasma enhanced chemical vapor deposition chamber, or   an atomic layer deposition chamber.   
     
     
         15 . The system of  claim 1 , wherein the process chamber comprises a plasma process chamber. 
     
     
         16 . A wafer holder to support a semiconductor wafer in a process chamber for performing a process for fabricating a three-dimensional integrated circuit, the wafer having a plurality of counterbore through holes from the back side of the wafer to the front side of the wafer, the wafer holder comprising a substantially rigid body configured so as to provide a substantially planar surface for contacting the back side of the semiconductor wafer; the wafer holder having a fluid flow channel in fluid communication with the planar surface, the wafer holder being configured for connection with a pump for applying a vacuum to the fluid flow channel to produce a pressure differential between the front side and back side of the semiconductor wafer; the wafer holder being configured so as to electrostatically clamp the wafer to the wafer holder; the substantially rigid body having a cavity and at least one structure disposed in the cavity and extending from the base of the cavity so as to form the planar surface; the structure having a knife edge for contacting the back side of the wafer so as to minimize the impedance of gas flow through the wafer; the wafer holder having a surface to form a seal at the back side periphery of the wafer. 
     
     
         17 . A wafer holder for a process to fabricate a three-dimensional integrated circuit, the wafer holder being configured to electrostatically hold the wafer and the wafer holder being configured to provide a vacuum at the back side of the wafer so as to produce a pressure differential between the front side of the wafer and the back side of the wafer during the process.