Enhancement-mode high-electron-mobility transistor and the manufacturing method thereof

Abstract

This invention discloses an enhancement-mode high-electron-mobility transistor and the manufacturing method thereof. The transistor comprises an epitaxial buffer layer on a substrate, a source and drain formed in the buffer layer, a PN-junction stack formed on the buffer layer and located between the source and drain, and a gate formed on the PN-junction stack, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor.

1 . An enhancement-mode high-electron-mobility transistor (HEMT) comprising:
 a buffer layer epitaxially formed on a semiconductor substrate;   a source and drain formed on the buffer layer;   a PN-junction stack formed on the buffer layer and located between the source and drain, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor; and   a gate formed on the PN-junction stack.   
     
     
         2 . The enhancement-mode HEMT of  claim 1 , wherein the PN-junction stack is separate from the source and drain. 
     
     
         3 . The enhancement-mode HEMT of  claim 1 , wherein the semiconductor substrate is composed of GaAs, GaN, Si, SiC, or Sapphire. 
     
     
         4 . The enhancement-mode HEMT of  claim 1 , wherein the buffer layer is of layered structure. 
     
     
         5 . The enhancement-mode HEMT of  claim 1 , wherein the buffer layer is composed of GaAs, GaN, AlN, or AlGaN. 
     
     
         6 . The enhancement-mode HEMT of  claim 4 , wherein the buffer layer is a AlGaN/GaN/AlN or GaN/AlGaN/AlN/GaN/AlN layered structure. 
     
     
         7 . The enhancement-mode HEMT of  claim 1 , wherein the source and drain are composed of Ti, Al, W, Ni, or Au. 
     
     
         8 . The enhancement-mode HEMT of  claim 1 , wherein the PN junction is composed of GaAs, GaN, AlN, or AlGaN. 
     
     
         9 . The enhancement-mode HEMT of  claim 1 , wherein the gate is composed of Pb, Al, Ti, Au, WN 2 , or mixtures thereof. 
     
     
         10 . A method for fabricating an enhancement-mode HEMT comprising:
 providing a semiconductor substrate that is with a buffer layer thereon;   forming a PN-junction stack on the buffer layer, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor;   etching the PN-junction stack that is out of the predetermined area of a gate;   forming a source on one side of the PN-junction stack and a drain on the other side thereof, wherein both the source and drain are formed on the buffer layer; and   forming the gate on the PN-junction stack.   
     
     
         11 . The method of  claim 10 , wherein the PN-junction stack is separate from the source and drain. 
     
     
         12 . The method of  claim 10 , wherein the semiconductor substrate is composed of GaAs, GaN, Si, SiC, or Sapphire. 
     
     
         13 . The method of  claim 10 , wherein the buffer layer is of layered structure. 
     
     
         14 . The method of  claim 10 , wherein the buffer layer is composed of GaAs, GaN, AlN, or AlGaN. 
     
     
         15 . The method of  claim 13 , wherein the buffer layer is composed of AlGaN/GaN/AlN or GaN/AlGaN/AlN/GaN/AlN. 
     
     
         16 . The method of  claim 10 , wherein the source and drain are composed of Ti, Al, W, Ni, or Au. 
     
     
         17 . The method of  claim 10 , wherein the PN junction is composed of GaAs, GaN, AlN, or AlGaN. 
     
     
         18 . The method of  claim 10 , wherein the gate is composed of Pb, Al, Ti, Au, WN 2 , or mixtures thereof.