Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on the semiconductor substrate; a gate electrode formed over the gate insulating film; a first stress application layer formed over the gate electrode and applying stress to the channel forming region; a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region.

1 . A semiconductor device including a field effect transistor comprising:
 a semiconductor substrate including a channel forming region;   a gate insulating film formed at the channel forming region on the semiconductor substrate;   a gate electrode formed over the gate insulating film;   a first stress application layer formed over the gate electrode and applying stress to the channel forming region;   a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and   a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein an upper surface of the first stress application layer and an upper surface of the second stress application layer are formed to be in the same height.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the channel forming region is formed at a flat region of the semiconductor substrate and   the field effect transistor is a planar-type field effect transistor.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the first stress application layer applies compression stress to the channel forming region and the second stress application layer applies tensile stress to the channel forming region.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the gate electrode applies compression stress to the channel forming region.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the first stress application layer applies tensile stress to the channel forming region and the second stress application layer applies compression stress to the channel forming region.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein the gate electrode applies tensile stress to the channel forming region.   
     
     
         8 . The semiconductor device according to  claim 3 ,
 wherein the first stress application layer is a film having compression stress when the field effect transistor is an n-channel field effect transistor and is a film having tensile stress when the field effect transistor is a p-type field effect transistor, and   the second stress application layer is a film having tensile stress when the field effect transistor is the n-channel field effect transistor and is a film having compression stress when the field effect transistor is the p-type field effect transistor.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the channel forming region is formed at an convex semiconductor region protruding from a main surface of the semiconductor substrate, and   the field effect transistor is a fin-type field effect transistor.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein the gate electrode and the gate insulating film cover two facing side surfaces of the semiconductor region.   
     
     
         11 . The semiconductor device according to  claim 9 ,
 wherein the gate electrode and the gate insulating film cover two facing side surfaces and an upper surface of the semiconductor region.   
     
     
         12 . The semiconductor device according to  claim 9 ,
 wherein the first stress application layer applies compression stress to the channel forming region and the second stress application layer applies tensile stress to the channel forming region.   
     
     
         13 . The semiconductor device according to  claim 12 ,
 wherein the gate electrode applies compression stress to the channel forming region.   
     
     
         14 . The semiconductor device according to  claim 9 ,
 wherein the first stress application layer applies tensile stress to the channel forming region and the second stress application layer applies compression stress to the channel forming region.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein the gate electrode applies tensile stress to the channel forming region.   
     
     
         16 . The semiconductor device according to  claim 9 ,
 wherein the first stress application layer is a film having compression stress when the field effect transistor is an n-channel field effect transistor and is a film having tensile stress when the field effect transistor is a p-type field effect transistor, and   the second stress application layer is a film having tensile stress when the field effect transistor is the n-channel field effect transistor and is a film having compression stress when the field effect transistor is the p-type field effect transistor.   
     
     
         17 . The semiconductor device according to  claim 9 ,
 wherein the semiconductor region is formed to be separated from the semiconductor substrate through an insulating film.   
     
     
         18 . The semiconductor device according to  claim 9 ,
 wherein the semiconductor region is formed to be connected to the semiconductor substrate.   
     
     
         19 . A manufacturing method of a semiconductor device in which a field effect transistor is formed, comprising:
 forming a gate insulating film on a semiconductor substrate at a channel forming region of the semiconductor substrate including the channel forming region;   forming a gate electrode over the gate insulating film;   forming a first stress application layer applying stress to the channel forming region over the gate electrode;   forming a source/drain region on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and   forming a second stress application layer applying stress different from the first stress application layer to the channel forming region over the source/drain region in a region other than at least a region of the first stress application layer.   
     
     
         20 . The manufacturing method of the semiconductor device according to  claim 19 , further comprising:
 performing polishing processing of at least the first stress application layer or the second stress application layer from an upper surface thereof so that the upper surface of the first stress application layer and the upper surface of the second stress application layer becomes the same height after the process of forming the second stress application layer.   
     
     
         21 . The manufacturing method of the semiconductor device according to  claim 19 ,
 wherein a planar-type field effect transistor is formed as the field effect transistor by using the semiconductor substrate in which the channel forming region is formed on a flat region of the semiconductor substrate as the semiconductor substrate having the channel forming region.   
     
     
         22 . The manufacturing method of the semiconductor device according to  claim 19 ,
 wherein a fin-type a planar-type field effect transistor is formed as the field effect transistor by using a convex semiconductor region in which the channel forming region protrudes from a main surface of the semiconductor substrate as the semiconductor substrate having the channel forming region.   
     
     
         23 . A manufacturing method of a semiconductor device in which a field effect transistor is formed, comprising:
 forming a dummy gate insulating film on a semiconductor substrate at a channel forming region of the semiconductor substrate including the channel forming region;   forming a dummy gate electrode over the dummy gate insulating film;   forming an offset film over the dummy gate electrode;   forming a source/drain region at a surface layer portion of the semiconductor substrate at both sides of the dummy gate electrode and the offset film;   forming a second stress application layer applying stress to the channel forming region over the source/drain region in a region other than at least a region of the offset film;   forming a trench for a gate electrode by removing the offset film, the dummy gate electrode and the dummy gate insulating film;   forming an gate insulating film by covering a bottom surface of the trench for the gate electrode;   forming a gate electrode in a height near the middle of the depth of the trench for the gate electrode over the gate insulating film; and   forming a first stress application layer applying stress different from the first application layer to the channel forming region by filling the trench for gate electrode over the gate electrode.   
     
     
         24 . The manufacturing method of a semiconductor device according to  claim 23 , further comprising:
 performing polishing processing of at least the first stress application layer or the second stress application layer from an upper surface thereof so that the upper surface of the first stress application layer and the upper surface of the second stress application layer becomes the same height after the process of forming the second stress application layer.