Nonvolatile semiconductor memory device

Abstract

A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   a memory cell which is provided on the semiconductor substrate, including:
 first and second diffusion layers, 
 a first gate insulating film which is provided on a first channel region between the first and second diffusion layers, 
 a charge storage layer which is provided on the first gate insulating film, 
 a first inter-electrode insulating film which is in contacting with the charge storage layer, and 
 a control gate electrode which is provided on the first inter-electrode insulating film; and 
   a first peripheral transistor which is provided on the semiconductor substrate, including:
 third and fourth diffusion layers, 
 a second gate insulating film which is provided on a second channel region between the third and fourth diffusion layers, 
 a first lower electrode which is provided on the second gate insulating film, 
 a blocking insulating film in contact with the first lower electrode, 
 a second inter-electrode insulating film which is provided on the blocking insulating film and comprises the same material as the first inter-electrode insulating film, and 
 a first upper electrode which is provided on the second inter-electrode insulating film; 
   a second peripheral transistor which is provided on the semiconductor substrate, including:
 fifth and sixth diffusion layers, 
 a third gate insulating film which is provided on a second channel region between the fifth and sixth diffusion layers and thicker than the second gate insulating film, 
 a second lower electrode which is provided on the third gate insulating film, 
 the blocking insulating film in contact with the second lower electrode, 
 a third inter-electrode insulating film which is provided on the blocking insulating film and comprises the same material as the first inter-electrode insulating film, and 
 an second upper electrode which is provided on the third inter-electrode insulating film; 
   wherein the first lower electrode and the first upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film,   the second lower electrode and the second upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film, and   the first and second inter-electrode insulating films and the third insulating film include a high-permittivity material.   
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the blocking insulating film is HTO, and a thickness dBL thereof is
   5 [nm]≦ dBL ≦( dFG− 20)/3 [nm]
 
   where dFG represents a thickness [nm] of the charge storage layer.   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the blocking insulating film is a silicon nitride film, and a thickness dBL thereof is
   5 [nm]≦ dBL ≦( dFG− 20)/3 [nm]
 
   where dFG represents a thickness [nm] of the charge storage layer.   
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the high-permittivity material is metal oxide.   
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the memory cell is a memory cell in a NAND cell unit.   
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 1 , further comprising:
 a third peripheral transistor which is provided on the semiconductor substrate adjacent to the memory cell, including seventh and eighth diffusion layers,   a fourth gate insulating film which is provided on a second channel region between the seventh and eighth diffusion layers, and a thickness of the fourth gate insulating film is equal to that of the first gate insulating film,   a third lower electrode which is provided on the fourth gate insulating film,   a fourth inter-electrode insulating film which is directly contacted to the third lower electrode and comprises the same material as the first inter-electrode insulating film, and the third peripheral transistor not having the blocking insulating film,   a third electrode which is provided on the fourth inter-electrode insulating film.   
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein a thickness of the second gate insulating film is equal to that of the first gate insulating film.   
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the control gate electrode and the upper electrode include metallic silicide.   
     
     
         9 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the floating gate electrode and the first and second lower electrodes are made from a same material, and the first and second control gate electrodes and the upper electrode are made from a same material.   
     
     
         10 . A nonvolatile semiconductor memory device comprising
 a semiconductor substrate;   a memory cell which is provided on the semiconductor substrate, including:
 first and second diffusion layers, 
 a first gate insulating film which is provided on a first channel region between the first and second diffusion layers, 
 a charge storage layer which is provided on the first gate insulating film, 
 a dielectric film which is provided on the charge storage layer, and 
 a control gate electrode which is provided on the dielectric film; and 
   a peripheral transistor which is provided on the semiconductor substrate, including:   third and fourth diffusion layers,   a second gate insulating film which is provided on a second channel region between the third and fourth diffusion layers,   a first lower gate electrode which is provided on the second gate insulating film, and   a first upper gate electrode provided on the first lower gate electrode, and an all bottom surface of the first upper gate electrode contacting to the first lower gate electrode,   a third gate insulating film which is provided on a second channel region between the fifth and sixth diffusion layers and thicker than the second gate insulating film,   a second lower gate electrode which is provided on the second gate insulating film, and   a second upper gate electrode provided on the second lower gate electrode, and an all bottom surface of the second upper gate electrode contacting to the second lower gate electrode, and   wherein the dielectric film includes a high-permittivity material.   
     
     
         11 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein the charge storage layer is composed of nitride.   
     
     
         12 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein the high-permittivity material is metal oxide.   
     
     
         13 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein the memory cell is a memory cell in a NAND cell unit.   
     
     
         14 . The nonvolatile semiconductor memory device according to  claim 1 , further comprising:
 a third peripheral transistor which is provided on the semiconductor substrate adjacent to the memory cell, including seventh and eighth diffusion layers,   a fourth gate insulating film which is provided on a second channel region between the seventh and eighth diffusion layers, and a thickness of the fourth gate insulating film is equal to that of the first gate insulating film,   a third lower electrode which is provided on the fourth gate insulating film,   a second inter-electrode insulating film and comprises the same material as the first inter-electrode insulating film, and   a third electrode which is provided on the fourth inter-electrode insulating film,   wherein the third lower electrode and the third upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film.   
     
     
         15 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein a thickness of the second gate insulating film is equal to that of the first gate insulating film.   
     
     
         16 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein the control gate electrode and the gate electrode include metal silicide.   
     
     
         17 . The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein the charge storage layer and the first and second lower portion of the gate electrodes are made from a same material, and the control gate electrode and the first and second upper portion of the gate electrodes are made from a same material.