Sram bit cell with self-aligned bidirectional local interconnects

Abstract

Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

What is claimed is: 
     
         1 . An SRAM comprising:
 active silicon regions on a substrate;   gate electrodes over the active silicon regions; and   self-aligned local interconnects overlying portions of the gate electrodes and portions of the active silicon regions.   
     
     
         2 . The SRAM according to  claim 1 , further comprising a hard mask layer over portions of an upper surface of the gate electrodes where the self-aligned local interconnects do not contact the gate electrodes. 
     
     
         3 . The SRAM according to  claim 2 , further comprising:
 first vias exposing portions of the self-aligned local interconnects; and   a first pattern of metal tracks over the first vias, wherein the first vias connect the first pattern of metal tracks to the self-aligned local interconnects.   
     
     
         4 . The SRAM according to  claim 3 , further comprising:
 second vias exposing portions of the first pattern of metal tracks; and   a second pattern of metal tracks over the second vias, wherein the second vias connect the second pattern of metal tracks to the first pattern of metal tracks.   
     
     
         5 . The SRAM according to  claim 4 , further comprising:
 third vias exposing portions of the pattern of second metal tracks; and   a third pattern of metal tracks over the third vias, wherein the third vias connect the third pattern of metal tracks to the second pattern of metal tracks.   
     
     
         6 . The SRAM according to  claim 5 , wherein the self-aligned local interconnects extend in two directions perpendicular to each other. 
     
     
         7 . The SRAM according to  claim 6 , wherein the first pattern of metal tracks extend in a single direction. 
     
     
         8 . The SRAM according to  claim 7 , wherein the first pattern of metal tracks extend in a direction perpendicular to the second pattern of metal tracks. 
     
     
         9 . The SRAM according to  claim 8 , further comprising tungsten as the self-aligned local interconnect material. 
     
     
         10 . The SRAM according to  claim 1 , further comprising a high-k dielectric under each gate electrode. 
     
     
         11 . The SRAM according to  claim 1 , further comprising an interlayer dielectric (ILD) over the gate electrodes and active regions, wherein the self-aligned local interconnects are formed through the ILD. 
     
     
         12 . An SRAM comprising:
 active silicon regions on a substrate;   gate electrodes over the active silicon regions;   an interlayer dielectric (ILD) over the active silicon regions and gate electrodes;   self-aligned local interconnects formed through the ILD, overlying portions of the gate electrodes and portions of the active silicon regions; and   a hard mask layer over portions of an upper surface of the gate electrodes where the self-aligned local interconnects do not contact the gate electrodes.   
     
     
         13 . The SRAM according to  claim 12 , further comprising:
 a second ILD over the self-aligned local interconnects;   first vias through the second ILD, exposing portions of the self-aligned local interconnects; and   a first pattern of metal tracks over the second ILD and the first vias, wherein the first vias connect the first pattern of metal tracks to the self-aligned local interconnects.   
     
     
         14 . The SRAM according to  claim 13 , further comprising:
 a third ILD over the first pattern of metal tracks;   second vias through the third ILD, exposing portions of the first pattern of metal tracks; and   a second pattern of metal tracks over the third ILD and second vias, wherein the second vias connect the second pattern of metal tracks to the first pattern of metal tracks.   
     
     
         15 . The SRAM according to  claim 14 , further comprising:
 a fourth ILD over the second pattern of metal tracks;   third vias through the fourth ILD, exposing portions of the pattern of second metal tracks; and   a third pattern of metal tracks over the third vias, wherein the third vias connect the third pattern of metal tracks to the second pattern of metal tracks.   
     
     
         16 . The SRAM according to  claim 15 , wherein the self-aligned local interconnects extend in two directions perpendicular to each other. 
     
     
         17 . The SRAM according to  claim 16 , wherein the first pattern of metal tracks extend in a single direction. 
     
     
         18 . The SRAM according to  claim 17 , wherein the first pattern of metal tracks extend in a direction perpendicular to the second pattern of metal tracks. 
     
     
         19 . The SRAM according to  claim 18 , further comprising tungsten as the self-aligned local interconnect material. 
     
     
         20 . An SRAM comprising:
 six transistors on a substrate, each comprising a gate electrode over a high-k dielectric and source/drain regions;   a first interlayer dielectric (ILD) over the gate electrode and source/drain regions;   tungsten or copper self-aligned local interconnects formed through the first ILD, overlying portions of the gate electrodes and portions of the source/drain regions, and extending in two directions perpendicular to each other;   a nitride or oxide hard mask layer over portions of an upper surface of the gate electrodes where the self-aligned local interconnects do not contact the gate electrodes;   a second ILD over the self-aligned local interconnects;   first vias through the second ILD, exposing portions of the self-aligned local interconnects; and   a first pattern of metal tracks over the second ILD and the first vias, wherein the first vias connect the first pattern of metal tracks to the self-aligned local interconnects,   wherein the self-aligned local interconnects and first vias make all of the electrical connections for the gate electrodes, the source/drain regions, and the first pattern of metal tracks.