Manufacturing fan-out wafer level packaging

Abstract

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.

We/I claim: 
     
         1 . A Fan-out wafer level package, comprising:
 an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface;   a substrate having a cavity;   an adhesive layer positioned between a top surface of the cavity and the bottom surface of the integrated circuit;   a bump positioned proximate a top surface of the substrate, spaced apart from the integrated circuit; and   a redistribution layer configured to electrically couple the bond pad of the integrated circuit to the bump.   
     
     
         2 . The fan-out wafer level packaging of  claim 1 , wherein the adhesive layer comprises an adhesive glue. 
     
     
         3 . The fan-out wafer level packaging of  claim 1 , wherein the adhesive layer comprises double-sided tape. 
     
     
         4 . The fan-out wafer level packaging of  claim 1 , further comprising a first dielectric layer extending at least partially over the top surface of the integrated circuit, the first dielectric layer defining a bond pad via, wherein at least a portion of the redistribution layer contacts the bond pad of the integrated circuit through the bond pad via. 
     
     
         5 . The fan-out wafer level packaging of  claim 4 , further comprising a second dielectric layer extending at least partially over the redistribution layer, the second dielectric layer defining a redistribution via to the redistribution layer. 
     
     
         6 . The fan-out wafer level packaging of  claim 5 , further comprising a redistributed bond pad positioned at least partially within the redistribution via. 
     
     
         7 . The fan-out wafer level packaging of  claim 1 , wherein the redistribution layer defines a redistributed bond pad, and the bump is in direct contact with the redistribution layer. 
     
     
         8 . The fan-out wafer level packaging of  claim 1 , wherein a ratio of a thickness of the substrate to a difference between a width of the cavity and a width of the integrated circuit is greater than or equal to ¼.