Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays

Abstract

At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

1 . An address scheduling method, comprising:
 selecting a first bit line connected to first through k th  strings of multi-level cells, where “k” is a natural number greater than or equal to 2;   selecting and deselecting each of the strings sequentially from the first string to the k th  string; and   performing address scheduling on N pages of each multi-level cell in each of the selected strings sequentially from a bottom word line to a top word line, where N is a natural number.   
     
     
         2 . The address scheduling method of  claim 1 , wherein the first through k th  strings are part of a non-volatile memory device with a three-dimensional (3D) memory cell array including a plurality of multi-level cells each configured to store up to N bits where N is a natural number greater than or equal to 2. 
     
     
         3 . The address scheduling method of  claim 2 , further comprising:
 selecting a second bit line connected to first through m th  strings of multi-level cells after the performing address scheduling is completed on all the pages of the multi-level cells connected to the first bit line, where “m” is a natural number greater than or equal to 2;   selecting and deselecting each of the strings connected to the second bit line sequentially from the first string to the m th  string; and   performing address scheduling on N pages of each multi-level cell in each of the selected strings connected to the second bit line from a bottom word line to a top word line, where N is a natural number.   
     
     
         4 . The address scheduling method of  claim 2 , wherein the address scheduling method is performed during programming of the 3D memory cell array. 
     
     
         5 . The address scheduling method of  claim 2 , wherein the non-volatile memory device includes at least one of a NAND and NOR flash memory device. 
     
     
         6 . An address scheduling method, comprising:
 selecting a first bit line connected to first through k th  strings of multi-level cells, where “k” is a natural number greater than or equal to 2;   selecting and deselecting each of first word lines sequentially from a first bottom word line to a first top word line; and   performing address scheduling on N pages of each multi-level cell connected to each of the selected first word lines sequentially from the first to k th  string, where N is a natural number.   
     
     
         7 . The address scheduling method of  claim 6 , wherein the first to k th  strings are part of a non-volatile memory device with a three-dimensional (3D) memory cell array including a plurality of multi-level cells each configured to store up to N bits where N is a natural number greater than or equal to 2. 
     
     
         8 . The address scheduling method of  claim 7 , further comprising:
 selecting a second bit line connected to first through m th  strings of multi-level cells after the performing address scheduling is completed on all of the pages of the multi-level cells connected to the first bit line, where “m” is a natural number greater than or equal to 2;   selecting and deselecting each of second word lines sequentially from a second bottom word line to a second top word line; and   performing address scheduling on N pages of each multi-level cell connected to each of the selected second word lines sequentially from the first to m th  string, where N is a natural number.   
     
     
         9 . (canceled) 
     
     
         10 . The address scheduling method of  claim 7 , wherein the address scheduling method is performed during programming of the 3D memory cell array. 
     
     
         11 . The address scheduling method of  claim 6 , wherein the non-volatile memory device is at least one of a NAND flash memory device and a NOR flash memory device. 
     
     
         12 . A non-volatile memory device with a three-dimensional (3D) memory cell array, comprising:
 a memory cell array including a plurality of multi-level cells each configured to store N bits, where N is a natural number greater than or equal to 2; and   a control circuit configured to control address scheduling of the memory cell array, including
 selecting a first bit line of the memory cell array, the first bit line connected to first through k th  strings of multi-level cells, where “k” is a natural number greater than or equal to 2, 
 selecting and deselecting each of the strings sequentially from the first string to the k th  string, and 
 performing address scheduling on N pages of each multi-level cell in each of the selected strings sequentially from a bottom word line to a top word line. 
   
     
     
         13 . The non-volatile memory device of  claim 12 , wherein the control circuit is configured to
 select a second bit line of the memory cell array after completing the address scheduling on all pages of multi-level cells connected to the first bit line, the second bit line connected to first through m th  strings of multi-level cells, where “m” is a natural number greater than or equal to 2,   select and deselect each of the strings connected to the second bit line sequentially from the first string to the m th  string, and   perform address scheduling on N pages of each multi-level cell in each of the selected strings connected to the second bit line from a bottom word line to a top word line.   
     
     
         14 . The non-volatile memory device of  claim 12 , wherein the control circuit is configured to perform address scheduling during programming of the memory cell array. 
     
     
         15 . A non-volatile memory device with a three-dimensional (3D) memory cell array comprising:
 a memory cell array including a plurality of multi-level cells each configured to store N bits, where N is a natural number greater than or equal to 2; and   a control circuit configured to control address scheduling of the memory cell array, including
 selecting a first bit line of the memory cell array, the first bit line connected to first through k th  strings of multi-level cells, where “k” is a natural number greater than or equal to 2, 
 selecting and deselecting each of first word lines sequentially from a first bottom word line to a first top word line, and 
 performing address scheduling on N pages of each multi-level cell connected to each of the selected first word lines sequentially from the first to k th  string. 
   
     
     
         16 . The non-volatile memory device of  claim 15 , wherein the control circuit is configured to
 select a second bit line of the memory cell array after the performing address scheduling is completed on all of the pages of the multi-level cells connected to the first bit line, the second bit line connected to first through m th  strings of multi-level cells, where “m” is a natural number greater than or equal to 2,   select and deselect each of second word lines sequentially from a second bottom word line to a second top word line, and   perform address scheduling on N pages of each multi-level cell connected to each of the selected second word lines sequentially from the first to m th  string.   
     
     
         17 . The non-volatile memory device of  claim 15 , wherein the control circuit is configured to perform address scheduling during programming of the 3D memory cell array. 
     
     
         18 . A memory system comprising:
 the non-volatile memory device of  claim 12 ; and   a memory controller configured to control the non-volatile memory device.   
     
     
         19 . A solid state drive (SSD) comprising the memory system of  claim 18 . 
     
     
         20 . A data storage apparatus comprising:
 a plurality of memory modules in a redundant array of independent disks (RAID), each of the memory modules including a plurality of three-dimensional (3D) non-volatile memory devices and a memory controller configured to control the operation of the 3D non-volatile memory devices, each of the 3D non-volatile memory devices including
 a memory cell array including a plurality of multi-level cells configured to store N bits, where N a natural number greater than or equal to 2, and 
 a control circuit configured to control address scheduling of the memory cell array, the control circuit configured to
 select a first bit line of the memory cell array, the first bit line connected to first through k th  strings of multi-level cells, where “k” is a natural number greater than or equal to 2, 
 select and deselect each of first word lines sequentially from a first bottom word line to a first top word line, and 
 perform address scheduling on N pages of each multi-level cell connected to each of the selected first word lines sequentially from the first to k th  string; and 
 
   a RAID controller configured to control the operation of the memory modules.   
     
     
         21 . The data storage apparatus of  claim 20 , wherein the control circuit is configured to
 select a second bit line of the memory cell array after the address scheduling is completed on all of the pages of the multi-level cells connected to the first bit line, the second bit line connected to first through m th  strings of multi-level cells, where “m” is a natural number greater than or equal to 2,   select and deselect each of second word lines sequentially from a second bottom word line to a second top word line, and   perform address scheduling on N pages of each multi-level cell connected to each of the selected second word lines sequentially from the first to m th  string.   
     
     
         22 . (canceled)