Nonvolatile semiconductor memory device and method for manufacturing same
Abstract
A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.
Claims
exact text as granted — not AI-modified1 - 11 . (canceled)
12 . A method for manufacturing a nonvolatile semiconductor memory device, comprising:
forming a multilayer body by alternately stacking a plurality of dielectric films and a plurality of electrode films; forming a trench in the multilayer body, the trench extending in one direction orthogonal to the stacking direction; forming a charge storage film on an inner surface of the trench; burying a semiconductor member inside the trench; and dividing the charge storage film and the semiconductor member in the one direction.
13 . The method according to claim 12 , wherein the dividing includes:
forming a mask film; forming a line-and-space pattern extending in another direction being orthogonal to the stacking direction and crossing the one direction; reducing the width of the pattern; etching the mask film using the pattern as a mask; forming a sidewall on a side surface of the mask film after the etching; removing the mask film; and selectively removing the charge storage film and the semiconductor member by etching using the sidewall as a mask.
14 . The method according to claim 13 , wherein the selectively removing the charge storage film and the semiconductor member includes:
performing wet etching on the charge storage film; performing dry etching on the semiconductor member; and oxidizing the semiconductor member.
15 . The method according to claim 13 , wherein the selectively removing the charge storage film and the semiconductor member includes:
performing wet etching on the charge storage film; performing dry etching on the semiconductor member; and performing chemical dry etching on the semiconductor member under a condition that etching rate for the semiconductor member is higher than etching rate for the charge storage film.
16 . The method according to claim 12 , further comprising:
forming a lower gate electrode film on a substrate; forming a lower trench extending in the one direction in the lower gate electrode film; forming a lower gate dielectric film on an inner surface of the lower trench; burying a semiconductor member inside the lower trench; and dividing the lower gate dielectric film and the semiconductor member in the one direction, wherein the trench is formed immediately above the lower trench.
17 . The method according to claim 16 , wherein the dividing the lower gate dielectric film and the semiconductor member is performed by dry etching.
18 . The method according to claim 12 , further comprising:
forming an upper gate electrode film on the multilayer body; forming an upper trench immediately above the trench in the upper gate electrode film; forming an upper gate dielectric film on an inner surface of the upper trench; burying a semiconductor member inside the upper trench; and dividing the upper gate dielectric film and the semiconductor member in the one direction.
19 . The method according to claim 18 , wherein the dividing the upper gate dielectric film and the semiconductor member is performed by dry etching.
20 . The method according to claim 12 , further comprising:
dividing the electrode film by forming another trench extending in the one direction in a region of the multilayer body between the trenches; and burying a dielectric material in the other trench.Join the waitlist — get patent alerts
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