Copper line having self-assembled monolayer for ulsi semiconductor devices, and a method of forming same

Abstract

A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.

1 . A method for forming a self-assembled monolayer, comprising the steps of:
 modifying a surface of a semiconductor substrate to form hydrogen groups bonded at the surface of the semiconductor;   flowing Cl 2  gas and irradiating UV onto the semiconductor substrate having undergone surface modification so as to substitute chlorine groups for the hydrogen groups are bonded at the surface of the semiconductor substrate; and   flowing NH 3  gas onto the surface of the having the chlorine groups bonded at the surface of the semiconductor substrate so as to substitute amine groups for the chlorine groups bonded to the surface of the semiconductor substrate.   
     
     
         2 . The method according to  claim 1 , wherein the step of modifying the surface of the semiconductor substrate is achieved by sequentially dipping the surface of the semiconductor substrate into sequentially a piranha solution and into a diluted HF solution wherein the piranha solution is previously prepared by mixing H 2 SO 4  and H 2 O 2  together. 
     
     
         3 . The method according to  claim 1  further comprises the step of baking the resultant semiconductor substrate to stabilize a bonding structure of the amine groups to the surface of the semiconductor substrate, wherein the baking step is performed after the step of flowing the NH 3  gas. 
     
     
         4 . A copper line of a semiconductor device, comprising:
 an interlayer dielectric formed on a semiconductor substrate and having a metal line forming region;   a self-assembled monolayer formed on a surface of the metal line forming region;   catalytic particles adsorbed onto a surface of the self-assembled monolayer; and   a copper layer formed on the self-assembled monolayer having the catalytic particles adsorbed thereto so that the copper layer substantially fills in the metal line forming region.   
     
     
         5 . The copper line of a semiconductor device according to  claim 4 , further comprising a barrier layer formed between the surface of the metal line forming region and the self-assembled monolayer. 
     
     
         6 . The copper line of a semiconductor device according to  claim 4 , wherein the self-assembled monolayer comprises a material layer on a surface in which amine silane groups or thiol silane groups are bonded. 
     
     
         7 . The copper line of a semiconductor device according to  claim 4 , wherein the catalytic particles comprise any one of Au, Cu, Pt, Ni and admixtures thereof. 
     
     
         8 . The copper line of a semiconductor device according to  claim 4 , wherein the catalytic particles have a mean diameter of about 2˜3 nm. 
     
     
         9 . The copper line of a semiconductor device according to  claim 4 , wherein the catalytic particles are adsorbed at the surface of the semiconductor substrate at an mean adjacent interval of about 4˜7 nm. 
     
     
         10 . The copper line of a semiconductor device according to  claim 4 , wherein the copper layer includes a copper seed layer which is formed by using an electroless plating technique.