Data with appended crc and residue value and encoder/decoder for same

Abstract

A semiconductor chip is described having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between an instruction execution core and a memory controller; and, iii) an interconnect path that resides between a cache and a memory controller. The ECC decoder circuitry has an input register to receive data, CRC values associated with the data and residue information associated with the data.

1 . A method, comprising:
 performing the following with circuitry along a interconnect path on a computing system:
 receiving data, CRC values associated with said data and residue information associated with said data; 
 performing a logical operation on said received data to form a vector of data having less bits than said data; 
 generating second CRC values from said vector; 
 comparing said CRC values with said second CRC values and identifying an error in bit locations of said data as a consequence; and, 
 calculating a second residue from said data and calculating a difference between said residue and said second residue; 
 using said difference to correct an error in one of said bit locations. 
   
     
     
         2 . The method of  claim 1  wherein said generating of said second CRC values includes multiplying said vector with a generation matrix. 
     
     
         3 . The method of  claim 2  wherein said generation matrix's values are determined with a Hamming code. 
     
     
         4 . The method of  claim 1  wherein said method is performed at a location along said interconnect path between a memory and an instruction execution core. 
     
     
         5 . The method of  claim 1  wherein said method if performed at a location along said interconnect path between a cache and an instruction execution core. 
     
     
         6 . The method of  claim 1  wherein said method is performed at a location along said interconnect path between a memory and a networking interface. 
     
     
         7 . The method of  claim 1  wherein said method is performed at a location along said interconnect path between a memory and a non volatile storage device. 
     
     
         8 . A semiconductor chip having ECC decoder circuitry disposed along any of:
 i) a interconnect path that resides between an instruction execution core and a cache;   ii) a interconnect path that resides between an instruction execution core and a memory controller;   iii) an interconnect path that resides between a cache and a memory controller, said ECC decoder circuitry having an input register to receive data, CRC values associated with the data and residue information associated with the data.   
     
     
         9 . The semiconductor chip of  claim 8  wherein said semiconductor chip further comprises encoder circuitry that produces said encoded data, said CRC values and said residue. 
     
     
         10 . The semiconductor chip of  claim 8  wherein said ECC decoder comprises a circuit that implements a generation matrix. 
     
     
         11 . The semiconductor chip of  claim 8  wherein said values of said generation matrix are produced by a Hamming code. 
     
     
         12 . The semiconductor chip of  claim 8  wherein said ECC decoder is implemented at least partially with program code. 
     
     
         13 . The semiconductor chip of  claim 8  wherein said ECC decoder circuitry performs the following method:
 receiving said data, CRC values and residue information; 
 performing a logical operation on said data to form a vector of data having less bits than said data; 
 generating second CRC values from said vector; 
 comparing said CRC values with said second CRC values and identifying an error in bit locations of said data as a consequence; 
 calculating a second residue from said data and calculating a difference between said residue and said second residue; and, 
 using said difference to correct an error in one of said bit locations. 
 
     
     
         14 . A computing system comprising:
 a flat panel display;   a semiconductor chip having an instruction execution core, said semiconductor chip having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between circuitry that prepares data for execution by said instruction execution core and a memory controller; iii) an interconnect path that resides between a cache and a memory controller, said ECC decoder circuitry having an input register to receive data, CRC values associated with the data and residue information associated with the data.   
     
     
         15 . The computing system of  claim 14  wherein said semiconductor chip further comprises encoder circuitry that produces said encoded data, said CRC values and said residue. 
     
     
         16 . The computing system of  claim 14  wherein said ECC decoder comprises a circuit that implements a generation matrix. 
     
     
         17 . The computing system of  claim 14  wherein said values of said generation matrix are produced by a Hamming code. 
     
     
         18 . The computing system of  claim 14  wherein said ECC decoder is implemented at least partially with program code. 
     
     
         19 . The computing system of  claim 14  wherein said ECC decoder circuitry performs the following method:
 receiving said data, CRC values and residue information; 
 performing a logical operation on said data to form a vector of data having less bits than said data; 
 generating second CRC values from said vector; 
 comparing said CRC values with said second CRC values and identifying an error in bit locations of said data as a consequence; 
 calculating a second residue from said data and calculating a difference between said residue and said second residue; and, 
 using said difference to correct an error in one of said bit locations.