Initial-on scr device for on-chip esd protection

Abstract

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

1 . A semiconductor device for electrostatic discharge (ESD) protection, comprising:
 a semiconductor substrate;   an n-type well formed in the substrate;   a p-type metal-oxide-semiconductor (PMOS) transistor formed in the n-type well including a gate, the PMOS including a first diffused region and a second diffused region separated apart from the first diffused region;   a first n-type region formed in the n-type well and electrically connected to the first diffused region of the PMOS transistor; and   a second n-type region formed in the n-type well and electrically connected to the first diffused region of the PMOS transistor, wherein the first n-type region is separated apart from the second n-type region by the second diffused region of the PMOS;   wherein the gate of the PMOS transistor is kept at a reference voltage level to keep the PMOS transistor at an on state before an ESD event occurs.   
     
     
         2 . The device of  claim 1  further comprising a p-type region formed in the substrate and electrically connected to the second diffused region of the PMOS transistor. 
     
     
         3 . The device of  claim 2 , wherein the second diffused region of the PMOS transistor formed in the n-type well and the p-type region formed in the substrate are formed in an integral p-type area. 
     
     
         4 . The device of  claim 1 , wherein the second diffused region of the PMOS extends out of the n-type well. 
     
     
         5 . The device of  claim 1 , wherein the gate of the PMOS transistor is electrically connected to an ESD detection circuit. 
     
     
         6 . The device of  claim 5 , wherein the ESD detection circuit includes a resistor and a capacitor. 
     
     
         7 . A semiconductor device for electrostatic discharge (ESD) protection, comprising:
 a silicon controlled rectifier (SCR) including a semiconductor substrate and a well formed in the semiconductor substrate;   a p-type metal-oxide-semiconductor (PMOS) transistor formed in the well including a gate, the PMOS including a first diffused region and a second diffused region separated apart from the first diffused region;   a first doped region formed in the well and electrically connected to the first diffused region of the PMOS transistor;   a second doped region formed in the well and electrically connected to the first diffused region of the PMOS transistor, wherein the first doped region is separated apart from the second doped region by the second diffused region of the PMOS; and   a detection circuit electrically connected to the gate of the PMOS transistor for keeping the PMOS transistor at an on state before an ESD event occurs.   
     
     
         8 . The device of  claim 7 , wherein the gate of the PMOS transistor is kept at a reference voltage level by the detection circuit before an ESD event occurs. 
     
     
         9 . The device of  claim 7 , wherein the detection circuit includes a resistor and a capacitor. 
     
     
         10 . The device of  claim 7  further comprising a third doped region formed in the semiconductor substrate electrically connected to the second diffused region of the PMOS transistor. 
     
     
         11 . The device of  claim 10 , wherein the second diffused region of the PMOS transistor formed in the well and the third doped region formed in the semiconductor substrate are formed in an integral doped area. 
     
     
         12 . The device of  claim 7 , wherein the second diffused region of the PMOS extends out of the well.