Fabricating method of semiconductor device and semiconductor device fabricated using the same method

Abstract

A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

1 . A fabricating method of a semiconductor device, the method comprising:
 providing a substrate having a first region and a second region;   forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch;   forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch;   implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region;   forming a first trench by etching the first region between the plurality of first gates; and   forming a second trench by etching the second region between the plurality of second gates.   
     
     
         2 . The fabricating method as claimed in  claim 1 , wherein forming the first and second gates includes forming the first pitch to be greater than the second pitch. 
     
     
         3 . The fabricating method as claimed in  claim 2 , wherein forming the second trench includes simultaneously dry etching the first and second regions, dry etching in the second region being slower than dry etching in the first region. 
     
     
         4 . The fabricating method as claimed in  claim 1 , wherein implanting the etch rate adjusting dopant includes implanting elements of Group IV of the periodic table. 
     
     
         5 . The fabricating method as claimed in  claim 1 , wherein forming the first trench and the second trench includes:
 forming a first pre-trench in the first region between the plurality of first gates by dry etching;   forming a second pre-trench in the second region between the plurality of second gates by dry etching; and   performing wet-etching in each of the first and second pre-trenches to form the first trench and the second trench, respectively.   
     
     
         6 . The fabricating method as claimed in  claim 5 , wherein dry etching is isotropic dry etching. 
     
     
         7 . The fabricating method as claimed in  claim 5 , wherein implanting the etch rate adjusting dopant includes implanting the etch rate adjusting dopant to a same depth as a depth of the second pre-trench. 
     
     
         8 . The fabricating method as claimed in  claim 5 , wherein the wet etching includes using tetramethyl ammonium hydroxide (TMAH) or ammonium hydroxide. 
     
     
         9 . The fabricating method as claimed in  claim 1 , wherein the first trench and the second trench are formed to have a hexagonal profile. 
     
     
         10 . The fabricating method as claimed in  claim 1 , further comprising:
 forming a first SiGe epitaxial layer in at least a portion of the first trench; and   forming a second SiGe epitaxial layer in at least a portion of the second trench.   
     
     
         11 . The fabricating method as claimed in  claim 1 , wherein forming the plurality of second gates in the second region includes forming a SRAM. 
     
     
         12 . The fabricating method as claimed in  claim 1 , further comprising, after forming the plurality of first gates and the plurality of second gates, forming a lightly doped drain (LDD) in the first region and the second region, such that implanting the etch rate adjusting dopant is performed between forming the first/second gates and forming the LDD or performed after forming the LDD. 
     
     
         13 . The fabricating method as claimed in  claim 1 , wherein forming the second trench includes forming the second trench in the implanted region of the second region, such that the first and second trenches have a substantially same depth. 
     
     
         14 . The fabricating method as claimed in  claim 1 , wherein implanting the etch rate adjusting dopant is performed using a tilted implant. 
     
     
         15 . A fabricating method of a semiconductor device, the method comprising:
 providing a substrate having a first region and a second region, the second region having a higher density of gates thereon than the first region;   implanting an etch rate adjusting dopant into the second region, while blocking the first region; and   forming first and second trenches in the first and second regions, respectively, by dry etching.   
     
     
         16 . The fabricating method as claimed in  claim 15 , wherein implanting the etch rate adjusting dopant includes implanting elements from Group IV of the periodic table. 
     
     
         17 . The fabricating method as claimed in  claim 15 , wherein dry etching is isotropic dry etching. 
     
     
         18 . The fabricating method as claimed in  claim 15 , wherein implanting the etch rate adjusting dopant includes implanting the etch rate adjusting dopant to a same depth as a depth of the second trench. 
     
     
         19 . The fabricating method as claimed in  claim 15 , wherein dry etching in the first and second regions is performed simultaneously, and the etch rate adjusting dopant slowing down the dry etching in the second region. 
     
     
         20 . A fabricating method of a semiconductor device, the method comprising:
 providing a substrate having a first region and a second region;   forming a plurality of first gates in the first region of the substrate;   forming a plurality of second gates in the second region of the substrate, such that the second gates have a different pitch than the first gates;   implanting an etch rate adjusting dopant only into one of the first and second regions to form an implanted region between adjacent respective gates; and   etching the substrate to simultaneously form first and second trenches in the first and second regions, respectively, such that the first and second trenches are between adjacent respective gates and have a substantially same depth.   
     
     
         21 . A semiconductor device, comprising:
 a substrate having a first region and a second region defined therein;   a plurality of first gates spaced apart from each other at a first pitch in the first region;   a plurality of second gates spaced apart from each other at a second pitch different from the first pitch in the second region;   a first trench in the first region between the plurality of first gates;   a second trench in the second region between the plurality of second gates;   a first SiGe epitaxial layer in at least a portion of the first trench; and   a second SiGe epitaxial layer in at least a portion of the second trench, the first trench and the second trench having a same depth.