US2012092924A1PendingUtilityA1

Method of providing an erase activation energy of a memory device

35
Individually held — no corporate assignee on recordPriority: Mar 31, 2005Filed: Dec 13, 2011Published: Apr 19, 2012
Est. expiryMar 31, 2025(expired)· nominal 20-yr term from priority
Inventors:Michael VanbuskirkColin S. BillZhida LanTzu-Ning Fang
G11C 13/0014B82Y 10/00
35
PatentIndex Score
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Claims

Abstract

A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.

Claims

exact text as granted — not AI-modified
1 - 27 . (canceled) 
     
     
         28 . A system comprising:
 a processor and a memory for storing instructions, that when executed by the processor performs a method for an operation on a memory device comprising:   programming the memory device by providing a charged species from a passive layer of the memory device into an active layer of the memory device, wherein the memory device comprises first and second electrodes with the passive layer and the active each between the first and second electrodes, and wherein the programmed memory device is programmed for a first erase activation energy; and   providing for the programmed memory device a second erase activation energy greater than the first erase activation energy.   
     
     
         29 . The system of  claim 28 , wherein providing the second erase activation energy greater than the first erase activation energy comprises applying an electrical potential to the memory device. 
     
     
         30 . The system of  claim 29 , wherein the electrical potential applied to the memory device is sufficient to program the memory device. 
     
     
         31 . The system of  claim 30 , wherein the active layer comprises inorganic material. 
     
     
         32 . The system of  claim 31 , wherein the active layer comprises at least one of Cu 2 O, SiO 2 , Ta 2 O 5 , WO 3 , TiO 2 , and SiON, and mixtures thereof. 
     
     
         33 . The system of  claim 30 , wherein the active layer comprises organic material. 
     
     
         34 . The system of  claim 33 , wherein the active layer comprises at least one of polyimide, poly(arylene ether), benzocyclobutene, and parylene-F, and mixtures thereof. 
     
     
         35 . The system of  claim 30 , wherein the active layer comprises low conductive semiconductor material. 
     
     
         36 . The system of  claim 35 , wherein the active layer comprises at least one of poly(phenylene), poly(pyridine), poly(paraphenylene vinylene), polyacetylene, and polyrrole, and mixtures thereof. 
     
     
         37 . The system of  claim 30 , wherein the active layer comprises at least one of Cu 2 O, SiO 2 , Ta 2 O 5 , WO 3 , TiO 2 , SiON, polyimide, poly(arylene ether), benzocyclobutene, parylene-F, poly(phenylene), poly(pyridine), poly(para-phenylene vinylene), polyacetylene, and polyprrole, and mixtures thereof. 
     
     
         38 . The system of  claim 30 , wherein the passive layer comprises at least one of copper sulfide and silver sulfide and mixtures thereof. 
     
     
         39 . The system of  claim 28 , wherein providing for the programmed memory device the second erase activation energy greater than the first erase activation energy comprises providing that the temperature of the memory device is sufficient to provide that the second erase activation energy is greater than the first erase activation energy. 
     
     
         40 . The system of  claim 39 , wherein providing that the temperature of the memory device is sufficient to provide that the second erase activation energy is greater than the first erase activation energy comprises providing current through the memory device. 
     
     
         41 . The system of  claim 39 , wherein providing that the temperature of the memory device is sufficient to provide that the second erase activation energy is greater than the first erase activation energy comprises providing a programming time sufficient to provide that the second erase activation energy is greater than the first erase activation energy of the memory device. 
     
     
         42 . The system of  claim 39  and further comprising programming the memory device while providing that the temperature of the memory device is sufficient to provide that the second erase activation energy is greater than the first erase activation energy. 
     
     
         43 . The system of  claim 39 , wherein the active layer comprises inorganic material. 
     
     
         44 . The system of  claim 43 , wherein the active layer comprises at least one of Cu 2 O, SiO 2 , Ta 2 O 5 , WO 3 , TiO 2 , SiON, and mixtures thereof. 
     
     
         45 . The system of  claim 39 , wherein the active layer comprises organic material. 
     
     
         46 . The system of  claim 45 , wherein the active layer comprises at least one of polyimide, poly(arylene ether), benzocyclobutene, and parylene-F, and mixtures thereof. 
     
     
         47 . The method of  claim 39 , wherein the active layer comprises low conductive semiconductor material. 
     
     
         48 . The method of  claim 47 , wherein the active layer comprises at least one of poly(phenylene), poly(pyridine), poly(paraphenylene vinylene), polyacetylene, and polyrrole, and mixtures thereof. 
     
     
         49 . The system of  claim 39 , wherein the active layer comprises at least one of Cu 2 O, SiO 2 , Ta 2 O 5 , WO 3 , TiO 2 , SiON, polyimide, poly(arylene ether), benzocyclobutene, parylene-F, poly(phenylene), poly(pyridine), poly(para-phenylene vinylene), polyacetylene, and polyprrole, and mixtures thereof. 
     
     
         50 . The system of  claim 39 , wherein the passive layer comprises at least one of copper sulfide and silver sulfide and mixtures thereof. 
     
     
         51 . The system of  claim 39 , wherein providing for the programmed memory device a second erase activation energy greater than the first erase activation energy further comprises applying an electrical potential to the memory device. 
     
     
         52 . The system of  claim 51 , wherein the electrical potential applied to the memory device is sufficient to program the memory device. 
     
     
         53 . A write-once read-many times memory comprising first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes.

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