Fabrication method of active device array substrate

Abstract

A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode.

1 . A fabrication method of an active device array substrate, comprising:
 providing a substrate and a multi-tone mask;   forming a first metal material layer over the substrate;   forming a gate insulation material layer over the first metal material layer;   forming a channel material layer over the gate insulation material layer;   forming a second metal material layer over the channel material layer;   forming a first photoresist layer over the second metal material layer, and patterning the first photoresist layer using the multi-tone mask to form a first patterned photoresist layer, wherein the first patterned photoresist layer comprises a concave pattern, and a part of the second metal material layer is exposed by the first patterned photoresist layer;   performing a first removing process using the first patterned photoresist layer as a mask to remove the second metal material layer, the channel material layer, the gate insulation material layer, and the first metal material layer not covered by the first patterned photoresist layer, so as to form a gate, a gate insulation layer, and a channel layer;   performing a second removing process to remove the concave pattern of the first patterned photoresist layer and the second metal material layer under the concave pattern, so as to form a source/drain and expose a part of the channel layer;   removing the first patterned photoresist layer;   forming a passivation layer over the substrate to cover a part of the substrate, the source/drain, and a part of the channel layer;   forming a second patterned photoresist layer over the passivation layer, wherein the passivation layer above the source/drain is exposed by the second patterned photoresist layer;   performing a third removing process using the second patterned photoresist layer as a mask to remove a part of the passivation layer and form a plurality of contact holes, so as to expose the source/drain;   forming a pixel electrode material layer over the passivation layer to cover the second patterned photoresist layer and the exposed source/drain; and   lifting off the second patterned photoresist layer to remove the pixel electrode material layer over the second patterned photoresist layer, so as to form a pixel electrode.   
     
     
         2 . The fabrication method according to  claim 1 , wherein the multi-tone mask comprises a half-tone mask. 
     
     
         3 . The fabrication method according to  claim 1 , wherein the first removing process further comprises over etching the first metal material layer to form an undercut concave at a side of the gate. 
     
     
         4 . The fabrication method according to  claim 1  further comprising forming a scan line electrically connected to the gate and a common line while forming the gate. 
     
     
         5 . The fabrication method according to  claim 4  further comprising forming a storage capacitance electrode above the common line while forming the source/drain. 
     
     
         6 . The fabrication method according to  claim 1  further comprising forming a plurality of first sub data line segments while forming the gate. 
     
     
         7 . The fabrication method according to  claim 6  further comprising forming a plurality of second sub data line segments along the extending direction of the first sub data line segments while forming the pixel electrode over the passivation layer, wherein one of the second sub data line segments is electrically connected to the source through the corresponding contact hole, and the second sub data line segments are electrically connected to the first sub data line segments to form a data line. 
     
     
         8 . The fabrication method according to  claim 7 , wherein the second sub data line segments are electrically connected between two of the first sub data line segments through a part of the contact holes of the passivation layer. 
     
     
         9 . The fabrication method according to  claim 1 , wherein the first removing process comprises a wet etching process. 
     
     
         10 . The fabrication method according to  claim 1 , wherein the second removing process comprises a dry etching process. 
     
     
         11 . The fabrication method according to  claim 1  further comprising forming an ohmic contact material layer over the channel material layer after forming the channel material layer. 
     
     
         12 . The fabrication method according to  claim 11 , wherein the second removing process further comprises removing a part of the ohmic contact material layer to form an ohmic contact layer. 
     
     
         13 . A fabrication method of an active device array substrate, comprising:
 providing a substrate and a multi-tone mask;   forming a first metal material layer over the substrate;   forming a gate insulation material layer over the first metal material layer;   forming a channel material layer over the gate insulation material layer;   forming a second metal material layer over the channel material layer;   forming a first photoresist layer over the second metal material layer, and patterning the first photoresist layer using the multi-tone mask to form a first patterned photoresist layer, wherein the first patterned photoresist layer comprises a concave pattern, and a part of the second metal material layer is exposed by the first patterned photoresist layer;   performing a first removing process using the first patterned photoresist layer as a mask to remove the second metal material layer, the channel material layer, the gate insulation material layer, and the first metal material layer not covered by the first patterned photoresist layer, so as to form a gate, a gate insulation layer, and a channel layer;   performing a second removing process to remove the concave pattern of the first patterned photoresist layer and the second metal material layer under the concave pattern, so as to form a source/drain and expose a part of the channel layer;   removing the first patterned photoresist layer;   forming a passivation layer over the substrate to cover a part of the substrate, the source/drain, and a part of the channel layer;   forming a second patterned photoresist layer over the passivation layer, wherein the passivation layer above the source/drain is exposed by the second patterned photoresist layer;   performing a third removing process using the second patterned photoresist layer as a mask to remove a part of the passivation layer and form a plurality of contact holes, so as to expose the source/drain;   removing the second patterned photoresist layer; and   forming a pixel electrode over the passivation layer, wherein the pixel electrode is filled into the contact holes and is electrically connected to the drain.   
     
     
         14 . The fabrication method according to  claim 13 , wherein the multi-tone mask comprises a half-tone mask. 
     
     
         15 . The fabrication method according to  claim 13  further comprising forming a scan line electrically connected to the gate and a common line while forming the gate. 
     
     
         16 . The fabrication method according to  claim 15  further comprising forming a storage capacitance electrode above the common line while forming the source/drain. 
     
     
         17 . The fabrication method according to  claim 13  further comprising forming a plurality of first sub data line segments while forming the gate. 
     
     
         18 . The fabrication method according to  claim 17  further comprising forming a plurality of second sub data line segments along the extending direction of the first sub data line segments while forming the pixel electrode over the passivation layer, wherein one of the second sub data line segments is electrically connected to the source through the corresponding contact hole, and the second sub data line segments are electrically connected to the first sub data line segments to form a data line. 
     
     
         19 . The fabrication method according to  claim 18 , wherein the second sub data line segments are electrically connected between two of the first sub data line segments through a part of the contact holes of the passivation layer. 
     
     
         20 . The fabrication method according to  claim 13 , wherein the first removing process comprises a wet etching process. 
     
     
         21 . The fabrication method according to  claim 13 , wherein the second removing process comprises a dry etching process. 
     
     
         22 . The fabrication method according to  claim 13  further comprising forming an ohmic contact material layer over the channel material layer after forming the channel material layer. 
     
     
         23 . The fabrication method according to  claim 22 , wherein the second removing process further comprises removing a part of the ohmic contact material layer to form an ohmic contact layer. 
     
     
         24 . The fabrication method according to  claim 13 , wherein the step of forming the pixel electrode comprises:
 forming a pixel electrode material layer over the passivation layer to cover the passivation layer and the exposed source/drain;   forming a third patterned photoresist layer over the passivation layer; and   patterning the pixel electrode material layer using the third patterned photoresist layer as a mask to form the pixel electrode.