Package structure having embedded semiconductor component and fabrication method thereof

Abstract

A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

1 . A package structure having an embedded semiconductor component, comprising:
 a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;   a first insulating protection layer having a chip mounting area for the chip to be mounted thereon, wherein the chip is mounted on the chip mounting area via the active surface thereof;   a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads through solder bumps so as to form a plurality of joints between the connection columns and the solder bumps;   an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip and filling spaces between the joints; and   a built-up structure formed on the other surface of the first insulating protection layer and the connection columns.   
     
     
         2 . The structure of  claim 1 , wherein the chip is an active component or a passive component. 
     
     
         3 . The structure of  claim 1 , wherein the connection columns are in height flush with, higher than or lower than the first insulating protection layer. 
     
     
         4 . The structure of  claim 1 , wherein the built-up structure comprises at least a dielectric layer, a wiring layer formed on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer and electrically connecting the wiring layer, portions of the wiring layer being formed on the first insulating protection layer and the connection columns for electrically connecting to the connection columns. 
     
     
         5 . The structure of  claim 4 , further comprising a second insulating protection layer formed on the built-up structure and having a plurality of second openings through which portions of the wiring layer are exposed to function as conductive pads. 
     
     
         6 . The structure of  claim 5 , further comprising a plurality of solder balls disposed on the conductive pads, respectively. 
     
     
         7 . A fabrication method of a package structure having an embedded semiconductor component, comprising the steps of:
 providing a carrier board having two opposite surfaces and having a core layer, a first metal layer formed on two opposite surfaces of the core layer, a release layer formed on the first metal layer, and a second metal layer formed on the release layer;   performing a patterning process to form a plurality of connection columns on the second metal layer and expose portions of the second metal layer;   forming a first insulating protection layer on the exposed portions of the second metal layer, with the connection columns being exposed from the first insulating protection layer;   mounting at least a chip on the connection columns, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the electrode pads being electrically connected to the connection columns through a plurality of solder bumps, respectively;   forming an encapsulant on the first insulating protection layer to encapsulate the chip;   removing the carrier board; and   forming a built-up structure on the first insulating protection layer and the connection columns.   
     
     
         8 . The method of  claim 7 , wherein the connection columns are in height flush with, higher than or lower than the first insulating protection layer. 
     
     
         9 . The method of  claim 7 , wherein the chip is an active component or a passive component. 
     
     
         10 . The method of  claim 7 , wherein the built-up structure comprises at least a dielectric layer, a wiring layer formed on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer and electrically connecting the wiring layer, portions of the wiring layer being formed on the first insulating protection layer and the connection columns for electrically connecting to the connection columns. 
     
     
         11 . The method of  claim 10 , further comprising the step of forming a second insulating protection layer on the built-up structure, with portions of the wiring layer being exposed from the second insulating protection layer to function as conductive pads. 
     
     
         12 . The method of  claim 11 , further comprising the step of forming a plurality of solder balls on the conductive pads, respectively. 
     
     
         13 . The method of  claim 7 , when forming the first insulating protection layer, further comprising the step of forming a plurality of first openings in the first insulating protection layer for exposing the connection columns, respectively.