US2012119220A1PendingUtilityA1

Nitride semiconductor structure

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Assignee: GUO YIH-DERPriority: Aug 31, 2006Filed: Jan 20, 2012Published: May 17, 2012
Est. expiryAug 31, 2026(~0.1 yrs left)· nominal 20-yr term from priority
H10P 14/3416H10P 14/3216H10P 14/2901H10P 14/278H10P 14/271H10P 14/38C30B 25/02C30B 29/403C23C 14/021C23C 16/303C23C 14/0617C23C 16/0227C23C 16/01C23C 14/0005H01S 2304/12H10H 20/018
44
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Claims

Abstract

A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate.

Claims

exact text as granted — not AI-modified
1 . A nitride semiconductor substrate, comprising:
 an epitaxy substrate;   a patterned nitride semiconductor pillar layer formed on the epitaxy substrate;   a nitride semiconductor layer formed on the nitride semiconductor pillar layer; and   a mask layer covering surfaces of the nitride semiconductor pillar layer and the epitaxy substrate,   wherein the nitride semiconductor pillar layer comprises:
 a plurality of first patterned arranged hollow structures; and 
 a plurality of second patterned arranged hollow structures located among the first patterned arranged hollow structures, the second patterned arranged hollow structures having nano dimensions. 
   
     
     
         2 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a material of the nitride semiconductor layer comprises gallium nitride, aluminum nitride, indium nitride, gallium indium nitride, aluminum gallium nitride, or aluminum gallium indium nitride. 
     
     
         3 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a height of the first patterned arranged hollow structures ranges from 1 μm to 10 μm. 
     
     
         4 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a width of the second patterned arranged hollow structures ranges from 30 nm to 500 nm. 
     
     
         5 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a ratio of a distance among each of the first patterned arranged hollow structures to a width of each of the first patterned arranged hollow structures is more than or equal to 0.5. 
     
     
         6 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a material of the first patterned arranged pillars and the second patterned arranged pillars comprises a III-nitride. 
     
     
         7 . The nitride semiconductor substrate as claimed in  claim 6 , wherein the III-nitride comprises nitride of boron, aluminum, gallium, indium, thallium or combination thereof. 
     
     
         8 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a material of the epitaxy substrate comprises sapphire, silicon carbide, silicon, or gallium arsenide. 
     
     
         9 . The nitride semiconductor substrate as claimed in  claim 1 , wherein the first patterned arranged hollow structures are cyclically arranged. 
     
     
         10 . The nitride semiconductor substrate as claimed in  claim 1 , wherein the second patterned arranged hollow structures are regularly or randomly arranged. 
     
     
         11 . The nitride semiconductor substrate as claimed in  claim 1 , wherein the first patterned arranged hollow structures have a stripe-shaped arrangement, a dot-shaped arrangement, or a meshed arrangement. 
     
     
         12 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a material of the mask layer comprises a dielectric material. 
     
     
         13 . The nitride semiconductor substrate as claimed in  claim 1 , wherein a nitride semiconductor freestanding substrate is formed by performing a separation process on the nitride semiconductor substrate when a thickness of the nitride semiconductor layer is more than 50 μm.

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