Semiconductor device and method of manufacturing the same

Abstract

Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

1 . A semiconductor device, comprising:
 a first semiconductor region of a first conductivity type disposed at a side of a first electrode;   a second semiconductor region having pairs of first regions of the first conductivity type, and second regions of a second conductivity type alternately provided along a surface at a side of a second electrode disposed at a side opposite said first electrode; and,   wherein   said second regions are formed by filling a semiconductor of the second conductivity type in each of said trenches formed in said second semiconductor region through epitaxial growth,   said first regions are formed as regions each located between two second regions, and   said control electrodes are arranged in stripe shapes so as to intersect at approximately an angle of 45° with a longitudinal direction of the stripes of said second regions.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 said second regions are each substantially identical in width and are arranged having approximately a same depth position; and   said control electrodes are substantially identical in width and are arranged having approximately a same depth position.   
     
     
         3 . A semiconductor device, comprising:
 a first semiconductor region of a first conductivity type disposed at a side of a first electrode;   a second semiconductor region having pairs of first regions of the first conductivity type, and second regions of a second conductivity type alternately provided at a side of a second electrode disposed at a side opposite said first electrode of said first semiconductor region; and,   wherein   said second regions are formed by filling a semiconductor of the second conductivity type in each of said trenches formed in said second semiconductor region through epitaxial growth,   said first regions are formed as regions located between two second regions,   each of said trenches composing said second regions is formed so that a (110) plane orientation appears in a sidewall of each of said trenches, and   each of said trenches composing said control electrodes is formed so that a (100) plane orientation appears in a sidewall of each of said trenches.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein each of said control electrodes has a first stripe-like arrangement which intersect at approximately an angle of 45° with the longitudinal direction of the stripe of said second region, and a second stripe-like arrangement which intersect at approximately an angle of 45° with the longitudinal direction of the stripe of said second region. 
     
     
         5 . The semiconductor device according to  claim 3 , wherein
 said second regions are substantially identical in width and arrangement pitch in the arrangement direction and are located at approximately a same depth position; and   said control electrodes are substantially identical in width and arrangement pitch in the arrangement direction and are located at approximately a same depth position.   
     
     
         6 . A semiconductor device, comprising:
 a first semiconductor region of a first conductivity type disposed at a side of a first electrode;   a second semiconductor region having pairs of first regions of a first conductivity type, and second regions of a second conductivity type alternately provided at a side of a second electrode disposed on a side opposite to said first electrode of said first semiconductor region; and   wherein   said second regions are formed by filling a semiconductor of the second conductivity type in each of said trenches formed in said second semiconductor region through epitaxial growth,   said first regions are formed as regions located between each two second regions,   said control electrodes are arranged in a stripe pattern so as to intersect with the said second regions, and   a crystal plane orientation appearing in a sidewall of each of said trenches composing said control electrodes is a crystal plane orientation which is higher in carrier mobility when an impurity is implanted than a crystal plane orientation appearing in a sidewall of each of said trenches composing the second regions.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein
 said second regions are substantially identical in width and arrangement pitch in the arrangement direction and located at substantially a same depth; and   said control electrodes are substantially identical in width and arrangement pitch in the arrangement direction and located at substantially a same depth.   
     
     
         8 . A method of manufacturing a semiconductor device, comprising:
 forming a second semiconductor region of a first conductivity type on a first semiconductor region of the first conductivity type;   forming first trenches having the same depth and the same shape in the same direction in said second semiconductor region, thereby forming first regions of the first conductivity type;   filling a semiconductor of a second conductivity type in each of said trenches through epitaxial growth, thereby forming second regions of the second conductivity type; and   wherein   in the step of forming said first trenches and in the step of forming said second trenches, said control electrodes are arranged in a stripe pattern so as to intersect with said second pillar regions, and   a crystal plane orientation appearing in said sidewall of each of said second trenches becomes a crystal plane orientation which is higher in carrier mobility when an impurity is implanted than a crystal plane orientation appearing in said sidewall of each of said first trenches.   
     
     
         9 . The semiconductor device according to  claim 1 , further comprising a third semiconductor region of the second conductivity type formed on a surface portion on a side of said second electrode of said second semiconductor region; and
 a fourth semiconductor region of the first conductivity type formed on a part of a surface of said third semiconductor region so as to be connected to said second electrode.   
     
     
         10 . The semiconductor device according to  claim 9 , further comprising control electrodes each provided within a trench and being separated by an insulating film, a sidewall of said trench being formed so as to contact each of said third semiconductor region and said fourth semiconductor region. 
     
     
         11 . The semiconductor device according to  claim 9 , wherein the second regions are arranged in a stripe pattern in a common direction in an element portion having said third semiconductor region and said fourth semiconductor region disposed therein. 
     
     
         12 . The semiconductor device according to  claim 3 , wherein a third semiconductor region of the second conductivity type is formed at a surface portion at a side of said second electrode of said second semiconductor region; and
 a fourth semiconductor region of the first conductivity type formed at a part of a surface of said third semiconductor region so as to be connected to said second electrode.   
     
     
         13 . The semiconductor device according to  claim 3 , further comprising control electrodes each provided within a trench and being separated by an insulating film, a sidewall of said trench being formed so as to contact each of said third semiconductor region and said fourth semiconductor region. 
     
     
         14 . The semiconductor device according to  claim 3 ,
 wherein the second regions are arranged in stripe shapes in a common direction in an element portion having said third semiconductor region and said fourth semiconductor region disposed therein.   
     
     
         15 . The semiconductor device according to  claim 6 , further comprising a third semiconductor region of the second conductivity type formed at a surface portion at a side of said second electrode of the second semiconductor region; and
 a fourth semiconductor region of the first conductivity type formed at a part of a surface of said third semiconductor region so as to be connected to said second electrode.   
     
     
         16 . The semiconductor device according to  claim 15 , further comprising control electrodes each provided within a trench and being separated by an insulating film, a sidewall of said trench being formed so as to contact each of said third semiconductor region and said fourth semiconductor region. 
     
     
         17 . The semiconductor device according to  claim 6 , wherein the second regions are arranged in a stripe pattern in a common direction in an element portion having said third semiconductor region and said fourth semiconductor region disposed therein. 
     
     
         18 . The method of manufacturing a semiconductor device according to  claim 8 , further comprising:
 forming a third semiconductor region of the second conductivity type at a surface portion on a side of a second electrode of said second semiconductor region; and
 forming a fourth semiconductor region of the first conductivity type at a part of a surface of said third semiconductor region. 
   
     
     
         19 . The method of manufacturing a semiconductor device according to  claim 8 , further comprising:
 forming second trenches having approximately a same depth and same shape in a common direction so that sidewalls of said second trenches contact each of said third semiconductor region and said fourth semiconductor region, forming an insulating film on said sidewall of each of said second trenches, and filling an electrode member in each of said second trenches, thereby forming control electrodes.