Trench Silicide Contact With Low Interface Resistance

Abstract

An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

1 . An electrical structure comprising:
 a dielectric layer present on a semiconductor substrate;   a via opening present through the dielectric layer;   an interconnect present within the via opening; and   a metal semiconductor alloy contact present in the semiconductor substrate, wherein the metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening, wherein endpoints for the convex curvature that define the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.   
     
     
         2 . The electrical structure of  claim 1 , wherein at least a portion of the metal semiconductor alloy contact extends from the interface between the via opening an the upper surface of the semiconductor substrate under the dielectric layer. 
     
     
         3 . The electrical structure of  claim 1 , wherein the metal semiconductor alloy contact comprises a silicide or germide. 
     
     
         4 . The electrical structure of  claim 3 , wherein the metal semiconductor alloy contact comprises nickel silicide (NiSi x ), nickel platinum silicide (NiPt y Si x ), cobalt silicide (CoSi x ), tantalum silicide (TaSi x ), and titanium silicide (TiSi x ). 
     
     
         5 . The electrical structure of  claim 1 , wherein the interconnect is composed of a metal. 
     
     
         6 . The electrical structure of  claim 5 , wherein the metal is selected from the group consisting of tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta) and combinations thereof. 
     
     
         7 . The electrical structure of  claim 1 , wherein the semiconductor substrate comprises a single crystal or polycrystalline material. 
     
     
         8 . The electrical structure of  claim 1 , wherein the electrical structure provides a contact to at least one of a source region and a drain region of a semiconductor device. 
     
     
         9 . A semiconductor device comprising:
 a gate structure on a channel portion of a semiconductor substrate;   a source region and a drain region on opposing sides of the channel portion of the semiconductor substrate;   a dielectric layer present on the semiconductor substrate, the source region, the drain region and the gate structure; and   an interconnect present extending through the dielectric layer into contact with a metal semiconductor alloy contact in electrical communication with at least one of the source region and the drain region, wherein the metal semiconductor alloy contact has a convex curvature that extends into at least one of the source region and the drain region, wherein endpoints for the convex curvature that define the metal semiconductor alloy contact are aligned to an interface between a sidewall of the interconnect and an upper surface of the semiconductor substrate.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the metal semiconductor alloy contact comprises a silicide or germide. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the metal semiconductor alloy contact comprises nickel silicide (NiSi x ), nickel platinum silicide (NiPt y Si x ), cobalt silicide (CoSi x ), tantalum silicide (TaSi x ), and titanium silicide (TiSi x ). 
     
     
         12 . The semiconductor device of  claim 10 , wherein the metal is selected from the group consisting of tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta) and combinations thereof. 
     
     
         13 . The semiconductor device of  claim 10 , wherein the gate structure comprises a high-k dielectric layer that is present on the channel portion of the semiconductor substrate, and a metal gate conductor that is present on the high-k dielectric layer. 
     
     
         14 . The semiconductor device of  claim 9 , wherein the metal semiconductor alloy contact is separated from the gate structure by a dimension ranging from 10 nm to 50 nm. 
     
     
         15 . The semiconductor device of  claim 9 , wherein a portion of the semiconductor substrate that is separating the metal semiconductor alloy contact from the gate structure is composed of single crystal or polycrystalline material. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the metal gate conductor is composed of TiN, TaN, Al, W or a combination thereof. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the gate structure has a width ranging from 10 nm to 100 nm. 
     
     
         18 . The semiconductor device of  claim 9 , wherein an adjacent semiconductor device is present on the semiconductor substrate separated from the semiconductor device by a pitch ranging from 60 nm to 200 nm. 
     
     
         19 . A method of forming a semiconductor device comprising:
 forming a gate structure on a channel portion of a semiconductor substrate, wherein a source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate;   forming a dielectric layer over the gate structure;   forming a via opening through the dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region;   forming an amorphous region in the semiconductor substrate by angled ion implantation through the via opening into the exposed surface of the semiconductor substrate;   removing the amorphous region to form a divot having a convex curvature relative to the centerline of the via opening;   forming a metal containing material on the divot; and   converting the metal containing material and a portion of the semiconductor substrate adjacent to the divot into a metal semiconductor alloy contact that has a convex curvature that extends into the at least one of the source region and the drain region, wherein endpoints for the convex curvature that define the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening and an upper surface of the semiconductor substrate; and   forming an interconnect within the via opening in direct contact with the metal semiconductor alloy contact.   
     
     
         20 . The method of  claim 19 , wherein the gate structure is formed using a replacement gate process. 
     
     
         21 . The method of  claim 19 , wherein the forming of the amorphous region in the semiconductor substrate by the angled ion implantation through the via opening into the exposed surface of the semiconductor substrate comprises implanting n-type dopants, p-type dopants, neutral conductivity type dopants, or a combination thereof. 
     
     
         22 . The method of  claim 19 , wherein a remaining portion of the semiconductor substrate that is not amorphous has a single crystal or polycrystalline crystal structure. 
     
     
         23 . The method of  claim 19 , wherein the forming of the metal containing material on the divot comprises a conformal deposition of a metal layer. 
     
     
         24 . The method of  claim 19 , wherein the converting of the metal containing material and the portion of the semiconductor substrate adjacent to the divot into a metal semiconductor alloy contact comprises thermal annealing, wherein a remaining portion of the metal containing material that is not converted to the metal semiconductor alloy contact is removed using a selective etch.