Test mode setting circuit

Abstract

Provided is a test mode setting circuit with a smaller number of terminals. A detector having a low threshold voltage and a detector having a high threshold voltage are provided to a test terminal for controlling a test mode of a semiconductor device, and the detector having the low threshold voltage releases a reset of a logic circuit while the detector having the high threshold voltage controls switching of the test mode. This configuration uses the test terminal, a reset terminal, and test mode control terminals in common between a normal state and a test state, thus reducing a large number of the terminals.

1 . A test mode setting circuit for controlling a test mode of a semiconductor device, comprising:
 a first detector having a first threshold voltage and including an input terminal connected to a test terminal;   a second detector having a second threshold voltage and including an input terminal connected to the test terminal; and   a logic circuit including a first input terminal connected to an output terminal of the first detector and a second input terminal connected to an output terminal of the second detector, for controlling the test mode of the semiconductor device based on output signals of the first detector and the second detector,   wherein a reset of the logic circuit is released when a voltage of the test terminal changes from a first power supply voltage to exceed the first threshold voltage of the first detector, to thereby set the semiconductor device to the test mode, and   wherein, in the test mode of the semiconductor device, when the voltage of the test terminal exceeds the second threshold voltage of the second detector, the logic circuit controls switching of a mode setting of the test mode.   
     
     
         2 . A test mode setting circuit according to  claim 1 , further comprising a latch connected between the output terminal of the first detector and the first input terminal of the logic circuit,
 wherein a reset of the latch is released when the voltage of the test terminal changes from the first power supply voltage to exceed the first threshold voltage of the first detector, and the latch is set when the voltage of the test terminal exceeds the second threshold voltage of the second detector, and thereby releases the reset of the logic circuit.   
     
     
         3 . A test mode setting circuit for controlling a test mode of a semiconductor device, comprising:
 a first detector having a first threshold voltage and including an input terminal connected to a test terminal;   a second detector having a second threshold voltage and including an input terminal connected to the test terminal;   a counter including a clock terminal connected to an output terminal of the second detector and a reset terminal connected to an output terminal of the first detector, for counting a signal input to the clock terminal; and   a logic circuit including a reset terminal connected to the output terminal of the first detector and an input terminal connected to an output terminal of the counter, for controlling the test mode of the semiconductor device based on output signals of the first detector and the counter,   wherein a reset of each of the counter and the logic circuit is released when a voltage of the test terminal changes from a first power supply voltage to exceed the first threshold voltage of the first detector, to thereby set the semiconductor device to the test mode, and   wherein in the test mode of the semiconductor device, the counter outputs a signal based on a signal output from the second detector, and the logic circuit controls switching of a mode setting of the test mode based on the signal output from the counter.   
     
     
         4 . A test mode setting circuit according to  claim 3 , further comprising a latch connected between the output terminal of the first detector and the reset terminals of the counter and the logic circuit,
 wherein a reset of the latch is released when the voltage of the test terminal changes from the first power supply voltage to exceed the first threshold voltage of the first detector, and the latch is set when the voltage of the test terminal exceeds the second threshold voltage of the second detector, and thereby releases the reset of the counter and the reset of the logic circuit.